ASIC DFT Technical Leader

Job Title

ASIC DFT Technical Leader

Role Summary

Lead design-for-test (DFT) strategy and execution for next-generation networking ASICs within the Silicon One development organization. Partner with front-end RTL, backend physical design, and validation teams to define and deliver DFT requirements, implementation, and post-silicon debug.

Experience Level

Senior — requires substantial experience; minimum 10 years of relevant DFT, test or silicon engineering experience as stated in the posting.

Responsibilities

Work across the RTL, physical design, and validation flows to ensure testability and quality through implementation and post-silicon phases.

• Define DFT architecture, requirements, and integration plan early in the design cycle.
• Collaborate with front-end RTL and backend physical design teams to implement scan, JTAG, BIST, and memory-BIST strategies.
• Drive ATPG and EDA tool flows (e.g., TestMax, Tetramax, Tessent) and support tool-based signoff activities.
• Lead gate-level simulation, timing-aware test verification, and debug using simulators (e.g., VCS).
• Plan and execute post-silicon validation and ATE pattern debug; work with P1687 where applicable.
• Contribute to DFT CAD, methodology, and infrastructure development and to DFT IP integration.
• Mentor engineers and coordinate cross-functional DFT reviews and handoffs.

Requirements

Must-have technical skills and experience for immediate contribution.

• 10+ years of hands-on experience in DFT, test, and silicon engineering (experience requirement; degree relocated to Education Requirements).
• Practical experience with JTAG protocols, scan architectures, BIST (including memory BIST) and boundary scan.
• Experience with ATPG and EDA test tool chains (TestMax, Tetramax, Tessent, PrimeTime or equivalent).
• Gate-level simulation and debugging experience using VCS or similar simulators.
• Post-silicon validation and ATE pattern experience; familiarity with P1687.
• Experience driving test-timing analysis and participating in signoff activities.

Nice-to-have:

• Verilog/SystemVerilog design experience for custom DFT logic and IP integration.
• DFT CAD tool/automation development and test methodology experience.
• Experience with SystemVerilog logic equivalency checking and functional verification practices.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering required.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).