ASIC DFT STA Engineer
The ASIC DFT STA Engineer performs static timing analysis (STA) and develops timing constraints for complex networking ASICs within the Common Hardware Group (CHG). The role partners with RTL, physical design, DFT, and validation teams to ensure timing closure through implementation and post-silicon validation.
Work focuses on timing constraint development and verification, DFT mode timing analysis, and supporting signoff activities for next-generation networking chips.
Senior β the posting specifies senior-level experience (examples in Education Requirements indicate ~7+ years with a Bachelor's or equivalent experience).
Primary responsibilities include analysis and ownership of timing across design and validation phases.
Must-have technical skills and experience.
Nice-to-have:
Minimum: Bachelor's degree + 7 years related experience, or Master's + 4 years, or PhD + 1 year. Preferred: Master's + 10 years. (The posting lists degree-plus-years combinations as the stated minimums.)
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).
