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ASIC DFT STA Engineer

Cisco Systems
August 17, 2026
Full-time
On-site
San Jose, California, United States
$167,700 - $245,200 USD yearly
Physical Design Jobs, Level - Senior

Job Title

ASIC DFT STA Engineer

Role Summary

The ASIC DFT STA Engineer performs static timing analysis (STA) and develops timing constraints for complex networking ASICs within the Common Hardware Group (CHG). The role partners with RTL, physical design, DFT, and validation teams to ensure timing closure through implementation and post-silicon validation.

Work focuses on timing constraint development and verification, DFT mode timing analysis, and supporting signoff activities for next-generation networking chips.

Experience Level

Senior β€” the posting specifies senior-level experience (examples in Education Requirements indicate ~7+ years with a Bachelor's or equivalent experience).

Responsibilities

Primary responsibilities include analysis and ownership of timing across design and validation phases.

  • Develop, verify, and debug timing constraints (SDC) and timing exceptions such as clock groups and exclusivity.
  • Perform static timing analysis and timing closure for implementation and signoff flows.
  • Analyze and debug timing for DFT modes (scan shift/capture, BIST) and post-silicon validation.
  • Collaborate with RTL, CDC/RDC, physical design, synthesis, and validation teams to resolve timing issues.
  • Communicate timing findings and reports clearly to cross-functional teams and stakeholders.

Requirements

Must-have technical skills and experience.

  • Proven experience with RTL-level design, CDC/RDC methodologies, and formal/conformal verification tools.
  • Experience developing and verifying timing constraints and performing STA.
  • Programming/scripting experience with at least two of: Perl, TCL, Python, Makefile.
  • Practical experience with SDC debugging and STA tool flows.
  • Strong analytical skills and ability to interpret complex timing reports.

Nice-to-have:

  • Experience debugging PCIe timing and TSMC memory timing constraints.
  • Experience with Synopsys PrimeTime/TCM and synthesis tools (Fusion/Design Compiler).
  • Experience with DFT tools and flows (Tessent, DFT insertion in RTL).

Education Requirements

Minimum: Bachelor's degree + 7 years related experience, or Master's + 4 years, or PhD + 1 year. Preferred: Master's + 10 years. (The posting lists degree-plus-years combinations as the stated minimums.)


About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

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Date Posted: 2026-08-17