ASIC DFT STA Engineer

Job Title

ASIC DFT STA Engineer

Role Summary

Join the Common Hardware Group (CHG) within Silicon One as an ASIC DFT/STA engineer focused on timing constraint development, static timing analysis (STA), and design-for-test (DFT) validation across block and full-chip flows. The role supports implementation flow and post-silicon validation and works closely with RTL, physical design, and verification teams.

Experience Level

Senior — the role expects substantial hands-on experience with STA and DFT flows; typical experience requirements in the posting indicate roughly 7+ years depending on academic qualification.

Responsibilities

Primary responsibilities include developing and validating timing constraints, performing STA checks, and improving STA/DFT processes.

• Develop timing constraints (SDC) at block, sub-chip, and full-chip levels, including test modes.
• Validate SDCs: check for duplicated constraints, unconstrained endpoints, no-clock endpoints, and proper promotion/demotion between block and top-level SDCs.
• Perform STA signoff activities and CDC/SDC validation; run and interpret timing and CDC checks.
• Support DFT timing modes (scan shift/capture, BIST) and post-silicon timing validation.
• Collaborate with RTL, synthesis, place-and-route, and verification teams to resolve timing issues and ensure closure.
• Develop methodologies, guidelines, and checklists to streamline STA work and improve flow robustness.

Requirements

Key must-have technical skills and experience; preferred items are listed afterward.

• Must-have: Hands-on experience with RTL-related design flows and timing constraint development and verification (SDC).
• Practical experience with CDC/RDC analysis and conformal verification flows.
• Proficiency in scripting/programming with at least two of: Perl, Tcl, Python, Makefile for automation and flow development.
• Experience performing STA checks, SDC validation, and interpreting timing reports to drive closure.
• Ability to collaborate across teams and communicate complex timing data clearly.
• Nice-to-have / Preferred: experience with PCIe and TSMC memory timing, DFT tooling and flows (Tessent), Synopsys signoff/STA tools (Primetime/TCM), and synthesis tools (Fusion/Design Compiler).

Education Requirements

Minimum academic/experience combinations specified in the posting: Bachelor's degree with 7+ years' related experience, Master’s degree with 4+ years' related experience, or PhD with 1+ year related experience. Preferred: Master’s degree with ~10 years' relevant experience. The posting does not specify particular fields of study or state an explicit "equivalent experience" clause.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).