ASIC DFT STA Engineer

Job Title

ASIC DFT STA Engineer

Role Summary

Member of the Common Hardware Group supporting Silicon One ASIC development. Responsible for static timing analysis (STA) and development/verification of timing constraints and DFT modes across implementation and post-silicon validation.

Work with RTL, physical design, DFT, and cross-functional teams to ensure timing closure and quality for networking chips.

Experience Level

Senior-level. Typical experience expectations: Bachelor's +7 years, Master's +4 years, or PhD +1 year of related experience.

Responsibilities

Key technical and delivery responsibilities:

• Develop, maintain, and verify timing constraints (SDC) for ASIC designs, including clock groups, exceptions, and clock exclusivity.
• Perform static timing analysis and debug timing closure issues across implementation flow and signoff stages.
• Drive DFT-related timing and quality processes during implementation and post-silicon validation (scan shift/capture, BIST).
• Collaborate with RTL, physical design, verification, and test teams to resolve CDC/RDC and timing interactions.
• Analyze and debug interface-specific timing (e.g., PCIe) and memory timing for target process nodes.
• Automate analysis and flows using scripting and tools; communicate results to engineering stakeholders.

Requirements

Must-have technical skills and experience are listed first, followed by preferred skills.

• Must-have: Practical experience with RTL design, CDC/RDC analysis and Conformal or equivalent verification tools.
• Experience developing and verifying SDC timing constraints and performing STA for complex ASICs.
• Programming/scripting experience with at least two of: Perl, TCL, Python, Makefile.
• Proven ability to analyze and debug timing issues and to work with cross-functional teams to implement fixes.
• Nice-to-have: Experience debugging PCIe timing and TSMC memory timing; experience with DFT timing closure (scan/BIST) and Tessent DFT insertion.
• Familiarity with STA tools such as Synopsys TCM/PrimeTime and synthesis tools like Synopsys Fusion/Design Compiler.

Education Requirements

Minimum qualifications specify degree-equivalent experience: Bachelor's degree with 7+ years, Master's degree with 4+ years, or PhD with 1+ year of related experience. Preferred listing also references a Master's degree with 10+ years. (Equivalent practical experience accepted per listed degree+experience combinations.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).