ASIC DFT Engineer - Acacia (Hybrid)

Job Title

ASIC DFT Engineer - Acacia (Hybrid)

Role Summary

Support Design-for-Testability (DFT) implementation, validation, and signoff for complex ASIC/SoC designs within Acacia, Cisco's optical interconnect silicon team. Work cross-functionally with RTL, verification, physical design, product engineering, and test teams to deliver manufacturable, high-coverage test solutions.

Experience Level

Mid-level; typically 3–7 years of relevant ASIC/DFT experience.

Responsibilities

Primary responsibilities include DFT implementation, validation, and supporting chip-level signoff.

• Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and test-mode logic.
• Run DFT rule checks and debug scan, clock, reset, and test-mode issues.
• Generate and validate ATPG patterns for stuck-at, transition, and other fault models; analyze coverage, pattern counts, and compression results.
• Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation failures.
• Support block-level and full-chip DFT integration, hierarchical DFT flows, and pattern retargeting/validation.
• Develop and maintain Tcl/Python/Perl/shell scripts to automate DFT flows and reporting.
• Collaborate with RTL, verification, physical design, product engineering, and test teams; support silicon debug and yield-learning as needed.

Requirements

Must-have technical skills and experience.

• Hands-on ASIC DFT implementation or validation experience.
• Experience with industry DFT tools (for example Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent).
• Practical knowledge of scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls.
• Experience with stuck-at and transition fault models and ATPG coverage analysis.
• Ability to debug scan-chain issues, DFT rule violations, and pattern simulation failures.
• Scripting experience in Tcl, Python, Perl, or shell for automation and reporting.
• Strong collaboration skills with cross-functional teams.

Nice-to-have:

• Hierarchical DFT methodology and block-level signoff experience.
• Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows.
• MBIST insertion, memory test validation, BISR, gate-level simulation, and SDF timing familiarity.
• Experience with silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug.
• Experience with advanced-node ASICs, networking ASICs, or high-performance SoCs and multi-clock-domain scan implementation.

Education Requirements

Bachelor's degree plus 5 years related experience, or Master's degree plus 3 years, or PhD with no required experience; or equivalent related work experience.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).