ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Lead design-for-test (DFT) programs for Broadcom ASICs from chip-level DFT specification through implementation, verification, silicon bring-up and release to production. Work as part of an SoC test team interfacing with physical design, STA, test engineering, manufacturing and customers.

Experience Level

Senior — role expects extensive experience; hiring guidance in posting: typically 12+ years with a Bachelor's degree or 10+ years with a Master's degree.

Responsibilities

Primary responsibilities include defining DFT strategy, implementing and verifying test logic, and supporting silicon debug and production testing.

• Define chip-level DFT specifications aligned to product test metrics and customer requirements.
• Implement DFT features: scan, MBIST, TAP, LBIST, IO/SerDes integration and other IP-level DFT.
• Insert scan and compression, generate and verify ATPG vectors, and validate vectors before tape-out.
• Perform pattern verification, ATE bring-up, and RMA/field-failure support.
• Collaborate with STA and physical design for DFT-mode timing closure.
• Assist silicon failure analysis, diagnostics and yield-improvement activities.
• Interface with customers and cross-functional teams globally during bring-up and debug.
• Automate DFT and test-vector generation flows and propose new DFT solutions for advanced nodes.

Requirements

Must-have technical skills and experience; listed items reflect required capabilities and important technical knowledge.

• Must-have: Strong DFT background (IO/analog DFT, ATPG/scan, BIST) and hands-on experience with scan insertion and compression tools (DFT Compiler, Mentor TestKompress or equivalent).
• Proven experience with ATPG vector generation, simulation and debugging (e.g., TetraMax, Fastscan).
• Verilog coding, testbench creation and simulation experience for test logic.
• Memory BIST insertion and verification experience for embedded memories (SRAM, CAM, eDRAM, ROM).
• Boundary-scan verification and test-vector generation; knowledge of IEEE 1149.1 and 1149.6.
• Familiarity with Test-STA and constraints related to DFT modes.
• Experience with IEE-1687/IJTAG, ICL and PDL for instrumentation and access.
• Solid understanding of analog and digital circuit design, device physics, silicon processing, logical/physical synthesis and transistor reliability.
• Strong debug, root-cause analysis, data-driven statistical process control and communication skills.
• Project management skills to prioritize deliverables across test engineering, reliability and operations teams.
• Nice-to-have: Direct ATE experience; SerDes, DDR, PCIe, Ethernet, CXL IOBIST verification and silicon debug; experience with Tessent SSN.

Education Requirements

Posting specifies either a Bachelor's degree with 12+ years of related experience, or a Master's degree with 10+ years of related experience. (No specific fields of study were listed.)

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.