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ASIC DFT Engineer

Cisco Systems
August 09, 2026
Full-time
On-site
Austin, Texas, United States
$165,000 - $241,400 USD yearly
DFT Jobs, Level - Senior

Job Title

ASIC DFT Engineer

Role Summary

Member of the Common Hardware Group (CHG) within Silicon One development, responsible for driving design-for-test (DFT) strategy and implementation across ASIC front-end RTL, back-end physical design, and post-silicon validation.

Work with cross-functional teams to develop DFT IP, integrate testability features into full-chip designs, and support test, debug, and diagnostic flows through implementation and production readiness.

Experience Level

Senior β€” requires at least 7 years of relevant experience.

Responsibilities

Key responsibilities include:

  • Design and implement hardware DFT features to support ATE, in-system test, debug, and diagnostics.
  • Develop and integrate DFT IP in collaboration with RTL, verification, and physical-design teams.
  • Drive DFT requirements early in the design cycle and ensure integration through implementation and post-silicon validation.
  • Collaborate on test strategy for new device models, bare die and stacked die, and promote reusable test and debug approaches.
  • Support gate-level simulation, test-timing validation, and physical-design signoff activities related to test logic.
  • Diagnose and debug silicon issues with minimal mentorship; coordinate with ATE and validation teams.

Requirements

Must-have and preferred technical skills:

  • Must-have: Significant hands-on experience in DFT, test, and silicon engineering.
  • Must-have: Experience with JTAG protocols, scan architectures, BIST (including memory BIST) and boundary scan.
  • Must-have: Experience with ATPG and EDA tools (examples: Tetramax, Tessent, TestMax) and static timing tools such as PrimeTime.
  • Must-have: Gate-level simulation and debugging experience using tools such as VCS or equivalent.
  • Must-have: Post-silicon validation and debug experience; familiarity with ATE patterns and P1687.
  • Nice-to-have: Verilog/SystemVerilog design experience for custom DFT logic and IP integration; functional verification familiarity.
  • Nice-to-have: DFT CAD development experience, test architecture and infrastructure development, and test static timing analysis.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required. The posting specifies at least 7 years of relevant experience. No certifications were specified.


About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

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Date Posted: 2026-08-08