Cisco Systems logo

ASIC DFT Engineer

Cisco Systems
August 16, 2026
Full-time
On-site
San Jose, California, United States
$165,000 - $241,400 USD yearly
DFT Jobs, Level - Senior

Job Title

ASIC DFT Engineer

Role Summary

Join the Common Hardware Group within Silicon One as an ASIC Design-for-Test (DFT) engineer. The role works across front-end RTL, backend physical design, and post-silicon validation to define and deliver DFT/IP, test strategies, and debug capabilities for high-performance networking ASICs.

Experience Level

Senior β€” requires at least 7 years of relevant experience in DFT, test, or silicon engineering.

Responsibilities

The role leads DFT strategy and implementation across the design and validation lifecycle.

  • Implement hardware DFT features to support ATE, in-system test, debug and diagnostics.
  • Develop and integrate DFT IP and test logic with RTL and full-chip integration flows.
  • Collaborate with front-end design, verification, and physical design teams to enable test integration and signoff.
  • Drive testability and debug strategies for bare die, stacked die, and new silicon device models.
  • Support post-silicon validation and debug activities, including ATE pattern work and diagnostics.
  • Provide technical leadership to craft solutions and debug issues with minimal mentorship.

Requirements

Must-have technical skills and tools experience; preferred items listed separately.

  • 7+ years of practical experience in DFT, test engineering, or silicon engineering.
  • Experience with JTAG protocols, scan architectures, BIST (including memory BIST) and boundary scan.
  • Proficiency with ATPG and EDA DFT toolsets (TestMax, Tetramax, Tessent) and timing tools such as PrimeTime.
  • Experience with gate-level simulation and debugging using VCS or similar simulators.
  • Post-silicon validation and debug experience; familiarity with ATE patterns and P1687 is required.
  • Strong debugging skills and ability to drive issues to resolution independently.

Preferred:

  • Verilog design experience for custom DFT logic and IP integration.
  • DFT CAD development experience: test architecture, methodology, and infrastructure.
  • Experience with Test Static Timing Analysis and SystemVerilog logic equivalency checking.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required. The posting specifies degree plus at least 7 years of experience.


About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

Cisco Systems logo

Date Posted: 2026-08-14