ASIC DFT Engineer

Job Title

ASIC DFT Engineer

Role Summary

Work within the Common Hardware Group (CHG) on Silicon One development as an ASIC DFT engineer. Collaborate with front-end RTL, backend physical design, and verification teams to define, implement, and validate design-for-test (DFT) features across the implementation and post-silicon validation flows.

Primary objectives include developing DFT IP, integrating testability features into full-chip designs, and supporting post-silicon debug and ATE workflows.

Experience Level

Senior — requires 7+ years of relevant experience.

Responsibilities

Deliver DFT architecture, IP, integration, and validation for high-performance networking ASICs.

• Define and implement DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop and integrate reusable DFT IP with RTL and physical design flows.
• Collaborate with RTL, verification, and physical design teams to ensure test logic integration through implementation and post-silicon phases.
• Drive DFT and quality processes during implementation, tapeout signoff, and post-silicon validation.
• Create test and debug strategies for new device models (bare die, stacked die) and multi-die packages.
• Debug complex silicon issues with limited mentorship and transfer learnings into design improvements.

Requirements

Technical skills and domain experience required for the role.

Must-have:

• Hands-on experience with JTAG, scan chains, and BIST architectures (including memory BIST and boundary scan).
• Experience with ATPG and DFT EDA tool flows (examples: TestMax, Tetramax, Tessent, PrimeTime).
• Gate-level simulation and debugging experience with simulators such as VCS.
• Post-silicon validation and debug experience; familiarity with ATE patterns and IEEE P1687 (IJTAG).
• Proven ability to craft DFT solutions and debug silicon issues independently.

Nice-to-have:

• Verilog/SystemVerilog design experience for custom DFT logic and IP integration.
• DFT CAD development and test architecture/methodology experience.
• Experience with test static timing analysis and test-timing validation.
• SystemVerilog-based verification skills and logic equivalency checking.

Education Requirements

Required: Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. The posting also specifies a minimum of 7 years of related experience.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).