ASIC Design Verification Engineer, DFT

Job Title

ASIC Design Verification Engineer, DFT

Role Summary

This role develops and verifies Design for Testability (DFT) architectures for custom ASICs and SoCs used in Meta's infrastructure. The engineer drives DFT verification closure across IP, sub-system, and SoC levels and collaborates with Design, DFT Architecture, Emulation, and Post-Silicon Validation teams to ensure manufacturability, testability, and first-pass silicon success.

Experience Level

Mid-level - typically requires 6+ years of hands-on ASIC design verification and DFT experience.

Responsibilities

Key responsibilities include:

• Define and implement DFT verification plans covering scan insertion, ATPG, BIST, JTAG, and boundary-scan structures at IP, sub-system, and SoC levels.
• Develop and maintain UVM- and C/C++-based testbenches to verify DFT logic such as scan chains and BIST controllers.
• Drive verification closure using metrics including functional coverage, code coverage, and DFT structural coverage goals.
• Collaborate with DFT architects and design engineers to review insertion methodologies and validate scan stitching and test access mechanisms.
• Debug and root-cause functional and structural failures in DFT logic and work with ATPG/design teams to resolve issues pre-silicon.
• Develop and validate ATPG test pattern generation flows to meet pattern quality and fault coverage targets.
• Apply formal verification techniques to prove correctness of DFT control logic and test-mode isolation.
• Partner with emulation and post-silicon teams to enable DFT bring-up and correlate pre-silicon results with silicon outcomes.
• Build and maintain verification infrastructure, scripts, and automation to improve efficiency and reuse.
• Contribute to continuous improvement of DFT verification methodologies, tools, and best practices.

Requirements

Must-have:

• 6+ years ASIC design verification using SystemVerilog and UVM-based methodologies.
• 6+ years of DFT verification experience: scan insertion, ATPG pattern validation, BIST verification, and JTAG/IEEE 1149.1.
• Experience with EDA tools for DFT insertion, ATPG, and simulation.
• Scripting proficiency for verification flow automation (Python, Tcl, Perl, or Shell).
• Experience driving IP, sub-system, or SoC-level verification closure, including test planning, testbench development, and coverage analysis.

Nice-to-have:

• Experience with formal verification applied to DFT control logic and test-mode isolation.
• Experience verifying high-speed interface DFT structures (PCIe, HBM, DDR, Ethernet SerDes).
• Experience with DFT for AI/ML accelerator or networking ASICs in data center environments.
• Experience with emulation platforms for DFT bring-up and pre-/post-silicon correlation.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a related technical field - or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.