ASIC Design Verification Engineer, DFT

Job Title

ASIC Design Verification Engineer - DFT

Role Summary

Join the Infrastructure Silicon organization to develop and verify Design-for-Testability (DFT) architectures for custom ASICs and SoCs used in data center infrastructure. The role focuses on ensuring silicon testability, manufacturability, and verification closure through collaboration with design, emulation, and post-silicon teams.

Experience Level

Mid-level - approximately 6 years of relevant ASIC verification and DFT experience.

Responsibilities

Deliver DFT verification across IP, subsystem, and SoC levels and drive closure to quality and fault-coverage targets.

• Define and execute DFT verification plans for scan insertion, ATPG, BIST, JTAG, and boundary-scan structures.
• Develop and maintain UVM-based and C/C++ testbenches for DFT logic verification and automation.
• Implement ATPG test pattern generation flows and validate patterns against fault coverage goals.
• Use functional and structural coverage metrics to drive verification closure.
• Debug and root-cause functional and structural failures in DFT logic; collaborate with design teams on fixes.
• Apply formal techniques to verify DFT control logic and test-mode isolation.
• Work with emulation and post-silicon validation teams for DFT bring-up and silicon correlation.
• Build and maintain verification infrastructure and automation to improve efficiency.
• Contribute to methodology and tool improvements for DFT verification.

Requirements

Must-have technical skills and proven experience relevant to DFT verification.

• Must-have: ~6 years hands-on ASIC design verification experience using SystemVerilog and UVM-based methodologies.
• Must-have: ~6 years of DFT verification experience, including scan insertion and ATPG pattern validation.
• Must-have: Proficiency with EDA tools for DFT insertion and simulation.
• Must-have: Scripting skills (Python, Tcl, Perl, or Shell) for automation and flows.
• Must-have: Experience driving IP, sub-system, or SoC-level verification closure.
• Must-have: Strong debugging skills for DFT logic and collaboration with design teams.
• Nice-to-have: Experience with C/C++ testbenches, emulation, post-silicon validation, and formal verification on DFT control logic.
• Nice-to-have: Knowledge of DFT structures for high-speed interfaces.

Education Requirements

Not specified.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.