ASIC Design Verification Engineer, DFT

Job Title

ASIC Design Verification Engineer, DFT

Role Summary

Work on DFT verification for custom ASICs and SoCs in Meta's Infrastructure Silicon team. Drive closure of DFT verification across IP, sub-system, and SoC levels to ensure manufacturability and first-pass silicon quality.

Experience Level

Senior - 8+ years of hands-on ASIC design verification experience, including SystemVerilog/UVM and DFT verification.

Responsibilities

Primary responsibilities include defining verification plans, building testbenches, and collaborating across design and validation teams to achieve verification closure.

• Define and implement DFT verification plans for scan insertion, ATPG, BIST, JTAG, and boundary scan at IP, sub-system, and SoC levels.
• Develop and maintain UVM-based and C/C++ testbenches to verify scan chains, memory BIST, and logic BIST controllers.
• Drive verification closure using metrics such as functional coverage, code coverage, and DFT structural coverage goals.
• Collaborate with DFT architects and design engineers to review insertion methodologies and validate scan stitching and test access mechanisms.
• Debug and root-cause functional and structural failures in DFT logic; coordinate fixes with design and ATPG teams.
• Develop and validate ATPG test pattern generation flows and ensure pattern quality and fault coverage targets are met.
• Apply formal verification to DFT control logic, scan enable paths, and test mode isolation where applicable.
• Partner with emulation and post-silicon validation teams for DFT bring-up and pre-/post-silicon correlation.
• Build and maintain verification infrastructure, scripts, and automation to improve efficiency and reuse across projects.

Requirements

Must-have skills and experience for immediate contribution, followed by preferred qualifications.

• Must-have: 8+ years of ASIC verification experience using SystemVerilog and UVM-based methodologies.
• Must-have: 8+ years of DFT verification experience including scan insertion, ATPG pattern validation, BIST verification, and JTAG/IEEE 1149.1.
• Must-have: Experience with EDA tools for DFT insertion, ATPG, and simulation.
• Must-have: Scripting proficiency in Python, Tcl, Perl, or Shell to automate verification flows.
• Must-have: Proven experience driving IP, sub-system, or SoC-level verification closure, including test planning, testbench development, and coverage analysis.
• Nice-to-have: Experience applying formal verification techniques to DFT control logic, scan enable paths, or test mode isolation.
• Nice-to-have: Experience with DFT for AI/ML accelerators or networking ASICs and with high-speed interface DFT (PCIe, HBM, DDR, Ethernet SerDes).
• Nice-to-have: Experience using emulation platforms for DFT bring-up and pre-/post-silicon correlation.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.