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ASIC Design Hardware Engineer - SDC/STA

Cisco Systems
September 28, 2026
Full-time
On-site
San Jose, California, United States
$155,000 - $222,600 USD yearly
Physical Design Jobs, Level - Mid-Career

Job Title

ASIC Design Hardware Engineer - SDC/STA

Role Summary

Work on Cisco Silicon One ASICs developing and validating timing constraints (SDC) and performing static timing analysis (STA) to achieve physical design closure. The role partners with front-end, back-end, DFT and architecture teams to produce block-level and full-chip SDCs and clocking documentation.

Experience Level

Mid-level. Cisco specifies degree + experience minimums (see Education Requirements); typical candidates meet the listed experience in ASIC SDC/STA, RTL, and scripting.

Responsibilities

Deliver and verify timing constraints and collaborate across design teams.

  • Develop block-level and full-chip SDCs for functional and test modes.
  • Validate SDCs using constraint-verification and STA tools (e.g., TCM, Timevision, PrimeTime).
  • Work with RTL and physical-design teams to identify and resolve timing issues across all design levels.
  • Contribute to full-chip clocking design, diagrams, and related documentation.
  • Help develop and apply methodologies to promote block SDCs to full-chip and to push down full-chip SDCs to blocks.
  • Review block SDCs and clocking diagrams and provide guidance to RTL/architecture owners.
  • Optionally perform block-level RTL design or IP integration as required.

Requirements

Must-have technical skills and experience needed to perform the responsibilities below.

  • Experience with STA and constraint tools (e.g., Synopsys PrimeTime) and synthesis tools (e.g., Synopsys DC/DCG/FC).
  • Strong HDL knowledge: Verilog/SystemVerilog.
  • Strong scripting skills; required experience with TCL; familiarity with Shell and Perl.
  • Solid understanding of digital design concepts: clocking, timing exceptions, asynchronous boundaries.
  • Proven experience with block and full-chip SDC development and timing closure across multiple timing modes.
  • Background in microarchitecture and RTL implementation.
  • Experience collaborating across front-end, back-end, and DFT teams to close timing.

Nice-to-have:

  • Effective technical documentation and cross-functional communication skills.
  • Demonstrated problem-solving, self-starting mindset, and ability to work in dynamic teams.

Education Requirements

Bachelor's degree in Electrical or Computer Engineering with 4+ years of ASIC or related experience, or Master's degree in Electrical or Computer Engineering with 2+ years of ASIC or related experience.


About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

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Date Posted: 2026-09-28