ASIC Design for Test Engineer

Job Title

ASIC Design for Test Engineer

Role Summary

The engineer will design and implement Design-for-Test (DFT) solutions for ASIC block and chip-level designs, focusing on achieving robust test coverage and validating generated test patterns. The role works with the customer team and cross-functional engineering groups to integrate DFT into the design and verification flow.

Experience Level

Mid-level. The posting specifies 5+ years of ASIC engineering experience.

Responsibilities

Key responsibilities include architecture, implementation, validation, and integration of DFT for ASICs.

• Architect and implement DFT solutions for block- and chip-level ASIC designs.
• Develop test timing constraints and generate test patterns for scan, MBIST, and related flows.
• Simulate and validate test patterns; measure and improve test coverage metrics.
• Work with static timing analysis and logic simulation tools to validate test timing and behavior.
• Collaborate with physical design, verification, and tool teams to integrate DFT into the design flow.

Requirements

Must-have technical skills and constraints; candidate must meet ITAR eligibility.

• 5+ years of experience as an ASIC engineer.
• Proven experience with DFT concepts: scan, scan compression, MBIST, BSCAN, and macro test development.
• Experience using internal and third-party DFT tool flows.
• Experience with Static Timing Analysis to validate test timing requirements.
• Experience with logic simulation tools for validating generated test patterns.
• Strong analytical, communication, and teamwork skills.
• ITAR eligibility required: U.S. Citizens or U.S. Permanent Residents only.

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering. Relevant coursework or background in digital/microprocessor design, computer architecture, and VLSI design is expected.

About the Company

Company: Shanghai Xiaoxi

Headquarters: Shanghai, China

Shanghai-based technology company recruiting FPGA design engineers to develop next-generation memory test platforms for AI systems, focusing on FPGA/RTL design, high-speed interfaces (DRAM, PCIe) and system-level test and validation.