ASIC Design Engineer - SoC Interconnect, Cache & Memory Systems

Job Title

ASIC Design Engineer - SoC Interconnect, Cache & Memory Systems

Role Summary

Join an SoC engineering team designing interconnects, cache controllers, memory subsystems and DDR memory controller components for high-performance, power-efficient silicon used in smartphones, PCs and automotive platforms.

The role partners with architects, verification, synthesis and physical-design teams to deliver RTL, support implementation activities, and debug pre- and post-silicon issues.

Experience Level

Mid-level. Guidance: approximately 0–4 years of industry or relevant academic experience.

Responsibilities

Design, implement, verify and support SoC interconnect and memory-related subsystems across the product lifecycle.

• Define microarchitecture and detailed design specifications for SoC interconnects, cache controllers and memory subsystems.
• Develop and validate RTL (Verilog/SystemVerilog) for interconnects, cache controllers and DDR/LPDDR memory controllers.
• Collaborate with system architects to assess feature feasibility and meet performance/power/area goals.
• Work with verification teams to create test plans, review coverage, debug functional issues and reach quality targets.
• Support synthesis, timing closure, power analysis, gate-level simulation and physical-design handoff.
• Participate in system-level integration, silicon bring-up and post-silicon debug.
• Contribute to C/C++ modeling, automation, and design methodology improvements.

Requirements

Key technical skills and practical experience required to perform the role.

• Must-have: Experience or coursework in Verilog and/or SystemVerilog RTL design, digital logic and computer architecture.
• Must-have: Hands-on experience or familiarity with SoC interconnects, cache/memory subsystem design, or DDR/LPDDR controller concepts.
• Must-have: Proficiency in C, C++ and/or Python for modeling, debug and tooling.
• Must-have: Familiarity with functional verification practices and coverage-driven verification techniques.
• Must-have: Understanding of synthesis, timing closure, physical-design support and power optimization workflows.
• Nice-to-have: Experience with Synopsys implementation tools, low-power design methodologies, ARM/x86 bus protocols, and post-silicon bring-up.
• Nice-to-have: Prior exposure to CPU, cache controller or memory controller RTL development.
• Strong analytical, communication and collaboration skills.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting also accepts relevant academic experience in place of equivalent industry experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.