ASIC Design Engineer, High Speed IO
Design RTL and micro-architecture for high-speed I/O IP blocks (UFS, Ethernet, PCIe, USB) used in next-generation automotive SoCs. The role covers end-to-end delivery: architecture trade-offs, RTL implementation, verification coordination, timing closure, and silicon validation.
The engineer will collaborate with hardware architects, verification, timing/VLSI and physical design teams across multiple locations to deliver routable, timing-closed IP suitable for production silicon.
Entry-level / Early career β recommended 2+ years of relevant ASIC RTL or digital design experience.
Accountable for the design, implementation, verification coordination and delivery of HSIO IP modules.
Key technical and team skills required and desirable for the role.
BTech or MTech in Electrical Engineering, Electronics & Communication Engineering (ECE) or a similar technical stream (as stated in the posting).
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
