ASIC Design Engineer (Hardware Security)
QualcommJob Title
ASIC Design Engineer (Hardware Security)
Role Summary
Design and deliver hardware security IP and subsystems for premium Snapdragon SoCs. Work across architecture, RTL design, verification, synthesis, timing closure and silicon bring-up to implement security features and countermeasures.
Member of the Hardware Security team collaborating with cross-functional groups (architecture, validation, layout, test) to produce secure, production-grade silicon.
Experience Level
Mid-level — typically requires extensive ASIC design experience (guidance: ~6+ years; see Education Requirements for degree-based variations).
Responsibilities
Key responsibilities include:
- Architect, RTL design (Verilog/SystemVerilog) and implement digital IP and subsystems focused on hardware security.
- Drive ASIC design flow tasks: microarchitecture, CDC handling, DFT integration, synthesis and timing closure.
- Collaborate with verification, layout, and validation teams; plan and execute silicon bring-up and testing.
- Integrate and debug bus interfaces, clocks/resets, and debug infrastructure.
- Contribute to security feature design (e.g., root of trust, RNG, crypto blocks) and countermeasure implementation.
- Provide technical leadership within cross-functional projects and document design and test plans.
Requirements
Must-have skills and experience; degree details summarized separately under Education Requirements.
- Significant ASIC design experience (guidance: 6+ years; see Education Requirements for degree-based alternatives).
- Proven RTL design using Verilog/SystemVerilog and familiarity with CDC, DFT, synthesis, and timing closure flows.
- Knowledge of bus protocols (AHB/AXI/others), clocks/resets, and debug methodologies.
- Experience with silicon validation, debug, and integration of complex subsystems.
- Strong problem-solving, written/verbal communication and teamwork skills; able to work with minimal supervision.
Nice-to-have:
- Experience with microcontroller CPUs, peripheral integration and system-level architecture.
- Background in mixed-signal integration, high-speed or low-power architecture, and area-optimized implementations.
- Hands-on experience in hardware security: root-of-trust, RNGs, symmetric/asymmetric crypto, side-channel mitigation, ECC, hardening.
- Verification, modeling and test-planning experience.
Education Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Mathematics or related technical field is minimum; Master's or PhD preferred. The posting specifies degree-based experience alternatives: Bachelor's +6 years, Master's +5 years, or PhD +4 years of relevant ASIC design/verification/validation/integration experience. Equivalent practical experience is accepted where stated.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
