ASIC Design Engineer - AI Accelerator

Role Summary

We are seeking an ASIC Design Engineer with intermediate to senior level experience to lead the architecture and development of our first-generation AI accelerator hardware. This position involves working on the entire ASIC design lifecycle from concept to silicon, ensuring it meets performance and efficiency standards in real-time machine learning applications.

Experience Level

This role is suited for candidates with 5 or more years of professional experience in ASIC or SoC design, ideally within a startup environment or in small teams where agility and innovation are paramount.

Responsibilities

• Lead the complete ASIC design process: architecture definition, RTL design, synthesis, verification, and chip bring-up.
• Collaborate with cross-functional teams including digital hardware, embedded software, and AI research for optimal design performance.
• Manage EDA tool operations, simulations, and timing analysis leading to the physical implementation of designs.
• Oversee external partnerships for fabrication, ensuring quality and precision in advanced fabrication processes (20 nm and below).
• Define and integrate critical IP blocks related to computation, memory subsystems, and interconnections.

Requirements

Applicants should have a Bachelor’s or Master’s degree in Electrical or Computer Engineering, with a PhD being advantageous. Proficiency in RTL design (Verilog/VHDL), synthesis, and timing closure is required. Familiarity with EDA tools like Synopsys, Cadence, or Mentor, along with knowledge of low-power digital design methodologies, is essential. Experience with advanced fabrication processes is also necessary.

Education Requirements

Bachelor’s or Master’s degree in Electrical or Computer Engineering; PhD is a plus.