ASIC Chip Lead

Job Title

ASIC Chip Lead

Role Summary

Lead end-to-end ASIC/System-on-Chip (SoC) development, from micro‑architecture and RTL through GDSII tape‑out and production. Manage cross‑functional engineering teams and coordinate with verification, physical design, firmware, systems, and operations to deliver silicon to a tier‑1 customer.

Experience Level

Senior - Principal level. Typically requires a decade or more of professional experience in microarchitecture and RTL design (see Education Requirements for degree guidance).

Responsibilities

Accountabilities across the ASIC lifecycle and cross‑discipline collaboration:

• Lead and coordinate cross‑functional project teams and communicate directly with a tier‑1 customer.
• Define micro‑architecture for design blocks and drive Verilog RTL development.
• Run frontend checks (lint, CDC, low‑power verification) and manage UPF/CPF flows.
• Collaborate with verification on test plans, coverage strategies, and closure.
• Coordinate with physical design on constraints and timing closure.
• Support firmware/systems during FPGA and silicon bring‑up and debugging.
• Work with operations to transition silicon into mass production.
• Adapt to project needs and perform tasks across design, verification, or bring‑up as required.

Requirements

Key technical skills and experience required and preferred.

• Must-have: Deep experience in RTL design and Verilog HDL; logic synthesis and static timing analysis; design verification and CDC handling.
• Must-have: Low‑power design techniques and practical use of UPF/CPF in multi‑power‑domain designs.
• Must-have: Familiarity with common on‑chip peripherals and interconnects (I2C, SPI, SPMI, UART, AHB, AXI) and memory controller integration.
• Must-have: Practical experience with EDA tools and flows; ability to read and act on microarchitecture and engineering specifications.
• Must-have: Strong written and verbal communication; ability to handle high‑stakes customer interactions and diffuse issues.
• Nice-to-have: ARM‑based SoC and DSP design experience; analog interface awareness.
• Nice-to-have: Experience with arithmetic hardware implementations, signal processing (MATLAB/Simulink), C/C++ and scripting (Perl/Tcl).
• Nice-to-have: Lab experience with logic analyzers and oscilloscopes; familiarity with AI tools for development productivity.

Education Requirements

Required: BSEE with 12+ years of experience, or MSEE with 10+ years of experience in microarchitecture and RTL design. Fields referenced include Electrical Engineering and related technical disciplines. No certifications were specified.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.