Architect, R&D Engineering — PrimeTime Static Timing Analysis

Job Title

Architect, R&D Engineering — PrimeTime Static Timing Analysis

Role Summary

Lead architect responsible for the PrimeTime static timing analysis (STA) platform. Work in an R&D team to define and implement architectural direction for timing engines, path search, constraint modeling, and distributed/parallel analysis to support sign-off at advanced nodes.

Collaborate with senior R&D leadership, cross-product teams, and customers to balance accuracy, scalability, performance, and usability in tapeout-critical flows.

Experience Level

Senior — typically requires 12+ years of experience in EDA, system software, or similarly demanding technical domains.

Responsibilities

Primary responsibilities include architecture, technical strategy, and resolution of tapeout-critical issues.

• Own and evolve major PrimeTime architectural components: timing engines, path search frameworks, constraint modeling, distributed/parallel analysis.
• Define long-term strategy for accuracy, capacity, runtime, memory footprint, and extensibility for STA.
• Drive consistency across PrimeTime, Fusion Compiler integration points, and the broader sign-off ecosystem.
• Lead design and implementation of next-generation STA algorithms for very large designs and advanced timing effects.
• Resolve cross-cutting technical issues and make tradeoffs between accuracy, performance, and usability at sign-off.
• Act as the technical authority for customer escalations and sign-off discrepancies.
• Diagnose systemic issues involving SDC interpretation, timing convergence, pessimism/optimism, and tool correlations.
• Mentor and influence engineers through reviews, technical guidance, and leadership.

Requirements

Must-have technical skills and experience:

• 12+ years of hands-on experience in EDA, system software, or equivalent technical domains.
• Deep practical experience with static timing analysis (STA) or closely related timing/circuit analysis.
• Expert-level proficiency in C/C++ on large, performance-critical codebases.
• Strong foundation in algorithms, data structures, and numerical analysis at scale.
• Proven experience architecting complex systems and driving multi-year technical initiatives.
• Ability to define, justify, and drive technical strategy and architectural decisions independently.

Nice-to-have:

• Experience with PrimeTime or other industry STA tools.
• Experience with distributed computing, parallel STA, and memory-scalable designs.
• Familiarity with advanced-node design challenges and sign-off flows.

Education Requirements

MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; or equivalent demonstrated industry expertise.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.