Architect, IP Verification — Noida
SynopsysJob Title
Architect, IP Verification — Noida
Role Summary
Senior ASIC digital verification engineer responsible for defining and implementing verification strategies and environments for Interface IP (PCIe, CXL, DDR, Ethernet, AXI) at the Noida site. Works with design and architecture teams to validate IP correctness and drive coverage closure.
The role includes hands-on development of SystemVerilog/UVM testbenches, simulation-based verification, and mentoring of junior verification engineers within a team focused on high-quality IP delivery.
Experience Level
Senior — typically 10+ years of relevant ASIC digital verification experience (role specifies MSEE with ~10+ years or BSEE with ~12+ years as typical guidance).
Responsibilities
Primary responsibilities include designing verification environments, executing verification plans, and collaborating across teams to ensure functional correctness.
- Design and implement verification environments for Interface IP protocols.
- Create and execute detailed test plans for complex ASIC designs.
- Develop and maintain verification IP and testbenches using SystemVerilog and UVM.
- Run simulations, analyze results, and debug design/verification issues using tools such as VCS or ModelSim.
- Perform functional coverage analysis and drive coverage closure.
- Collaborate with design and architecture teams to identify, reproduce, and resolve bugs.
- Mentor and guide junior verification engineers on best practices and methodologies.
Requirements
Key technical skills and attributes required for successful performance in this role.
- Must-have: Extensive ASIC digital verification experience with Interface IP protocols (PCIe, CXL, DDR, Ethernet, AXI).
- Must-have: Proficiency in SystemVerilog and UVM methodologies.
- Must-have: Experience with simulation tools such as VCS, ModelSim, or equivalent.
- Must-have: Strong understanding of digital design and verification concepts; excellent problem-solving and attention to detail.
- Must-have: Proven mentoring or leadership experience guiding junior engineers.
- Nice-to-have: Prior experience verifying complex interface IP at system or chip level; familiarity with formal or emulation flows.
Education Requirements
Bachelor of Science in Electrical/Electronics/VLSI Engineering (BSEE) with ~12+ years of relevant experience, or Master of Science in Electrical Engineering (MSEE) with ~10+ years of relevant experience. Equivalent practical experience may be considered.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
