Applications Engineering Sr. Static Timing Analysis Staff Engineer

Job Title

Applications Engineering Sr. Static Timing Analysis Staff Engineer

Role Summary

Senior applications engineer working with customer design teams to resolve static timing analysis (STA) and signoff challenges using PrimeTime on advanced-node designs. The role sits in Applications Engineering and partners with R&D and product teams to reproduce issues, drive tool and methodology improvements, and support production deployments.

Position hiring locations: Hyderabad or Bangalore (candidate availability). Work is customer-facing and tapeout-driven.

Experience Level

Senior. The posting does not specify a numeric years-of-experience requirement.

Responsibilities

Key responsibilities include hands-on STA support, debugging, and enabling customer signoff on advanced-node designs.

• Work directly with semiconductor customers to resolve timing closure and signoff challenges under tight tapeout schedules.
• Debug critical timing issues: setup and hold violations, clock domain crossings, SI-related timing failures, and variation-induced signoff problems using PrimeTime.
• Guide customers on MMMC analysis and OCV/AOCV/POCV variation-aware methodologies for 5nm and below nodes.
• Collaborate with R&D and product engineering to reproduce customer issues, identify root causes, and drive tool or methodology fixes.
• Develop reference flows and automation (Tcl; Python) and produce best-practice documentation for customer adoption.
• Deliver technical training sessions, workshops, and live demos covering PrimeTime capabilities and signoff methodologies.
• Promote adoption of PrimeTime signoff features via proofs-of-concept and production support.

Requirements

Must-have technical skills and experience; nice-to-have items are listed separately.

• Must-have: Strong hands-on experience with Synopsys PrimeTime for static timing analysis and signoff on production designs.
• Must-have: Deep understanding of timing constraints (SDC), MMMC frameworks, and variation-aware methodologies (OCV, AOCV, POCV).
• Must-have: Proven ability to diagnose and debug complex timing issues including setup/hold, CDCs, SI effects, and variability-driven failures.
• Must-have: Proficiency in Tcl scripting for tool automation and flow development.
• Must-have: Experience with advanced-node designs (5nm and below) and their signoff requirements.
• Must-have: Excellent customer-facing communication skills and ability to work under tapeout pressure.
• Nice-to-have: Python or Perl scripting experience for automation and tooling.

Education Requirements

Bachelor's degree in Electronics and Communication Engineering plus a Master's degree in VLSI, Embedded Systems, or Communication Systems as stated in the posting.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.