Applications Engineering, Sr Staff Engineer (Static Timing Analysis)
SynopsysJob Title
Applications Engineering, Sr Staff Engineer (Static Timing Analysis)
Role Summary
Senior field/solutions engineer responsible for driving adoption and deployment of static timing analysis (STA) workflows at customer sites, with a focus on Synopsys PrimeTime. The role combines hands-on debugging, technical evaluations, training, and collaboration with R&D and sales to resolve timing and signal-integrity issues for complex SoCs.
Experience Level
Senior - typically 8+ years of relevant experience (10+ years if holding only a Bachelor's degree). Proven tape-out and customer-facing field engineering experience expected.
Responsibilities
Provide technical leadership and hands-on support for timing sign-off and methodology adoption.
- Drive PrimeTime adoption from competitive benchmarks through production tape-out support on advanced-node designs.
- Lead technical evaluations comparing STA tools and present clear technical and business value to customers and management.
- Provide hands-on timing closure, ECO, and sign-off assistance; diagnose complex timing, SI, and variation issues.
- Develop and deliver technical training and methodology guidance for timing constraints, MMMC analysis, and variation modeling.
- Collaborate with R&D to reproduce field issues, communicate customer requirements, and influence product roadmap.
- Build and maintain TCL-based automation and methodology scripts to improve customer productivity and reduce escalations.
- Act as the technical interface between customers, sales, marketing, and engineering, converting pain points into actionable product feedback.
Requirements
Necessary technical skills and field experience for the role.
- Deep, hands-on experience with Synopsys PrimeTime: timing analysis, constraint development, and sign-off flows.
- Strong understanding of timing concepts: setup/hold analysis, clock domain crossing, multi-mode multi-corner, OCV/AOCV, and signal integrity effects.
- Proficiency in TCL scripting for automation, analysis, and methodology development in EDA environments.
- Familiarity with the digital design flow: synthesis, place-and-route, extraction, and ECO methodologies and how STA integrates into each phase.
- Proven ability to diagnose whether timing failures stem from constraints, tool settings, synthesis, or design issues.
- Excellent verbal and written communication for both engineers and management; prior customer-facing or field engineering experience is a strong plus.
- Willingness to travel to customer sites for evaluations, training, and critical design milestones.
Education Requirements
Bachelor's degree in Electrical Engineering (or equivalent) with 10+ years of relevant ASIC/SoC or EDA experience, or a Master's degree with 8+ years of relevant experience. Equivalent practical experience is explicitly acceptable.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
