Applications Engineering, Senior Engineer - FPGA, RTL Design & Emulation

Job Title

Applications Engineering, Senior Engineer - FPGA, RTL Design & Emulation

Role Summary

Provide field engineering and technical support for Synopsys Zebu emulation and Protocompiler prototyping products, focusing on FPGA partitioning, synthesis, place-and-route, and hardware debug. Work with global customers and R&D to resolve complex design bring-up and verification issues.

Support includes migrations to new releases, deploying features on live designs, delivering customer training, and participating in pre-sales evaluations and occasional onsite troubleshooting.

Experience Level

Senior. See Education Requirements for specific degree-and-years guidance; role expects experienced FPGA/RTL engineers who can diagnose and resolve complex hardware and toolflow issues.

Responsibilities

Provide technical field support and enable customer success across emulation and prototyping workflows.

• Troubleshoot customer issues across partitioning, synthesis, place-and-route, and hardware debug on Zebu and Protocompiler platforms.
• Migrate customer designs to new software releases and resolve regressions or performance issues.
• Deploy and validate new software features on customer designs (partitioning algorithms, debug modes, FPGA target updates).
• Deliver technical training ranging from basic tool usage to advanced multi-FPGA partitioning and hardware-software co-verification.
• Collaborate with HAV R&D to report issues, provide reproducible test cases, and advocate product improvements.
• Support pre-sales evaluations by running customer designs and demonstrating performance.
• Occasional travel to customer sites for onsite support, training, or critical issue resolution.

Requirements

Core technical skills and practical experience required for independent customer support and issue resolution.

• Hands-on FPGA logic design and implementation experience, including synthesis, place-and-route, and timing closure.
• Strong ability to read, debug, and modify RTL (Verilog/SystemVerilog or VHDL).
• Practical understanding of FPGA architecture, resource utilization, clock-domain crossing, and design partitioning.
• Experience analyzing synthesis logs, waveform dumps, and FPGA utilization reports to isolate root causes.
• Familiarity with hardware‑software integration and interface protocols such as PCIe, AXI, UART, or I2C (preferred).
• Scripting skills in Python, Tcl, or shell for automation and log analysis (desired).
• Good communication skills for working with customers under pressure and for producing clear reproducible problem reports for R&D.
• Experience with Xilinx or Intel/Altera synthesis tools, and familiarity with emulation/prototyping hardware/software, is a plus.

Education Requirements

Bachelor's in Electronics Engineering with 2–3 years of relevant experience, or Master's in Electronics Engineering with 1–2 years of relevant experience (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.