Skip to main content
Synopsys logo

Applications Engineering, Senior Engineer (FPGA, RTL Design & Emulation)

Synopsys
September 19, 2026
Full-time
On-site
Bengaluru, Karnataka, India
FPGA Programming Jobs, Level - Senior

Job Title

Applications Engineering, Senior Engineer (FPGA, RTL Design & Emulation)

Role Summary

Provide technical field support and training to customers using Synopsys emulation and prototyping solutions. Troubleshoot FPGA, RTL, synthesis, partitioning, and hardware debug issues and work with R&D to resolve product problems.

Customer-facing role supporting pre-sales evaluations, software migrations, feature deployment on customer designs, and occasional onsite support.

Experience Level

Senior. The posting title is Senior Engineer. The posting provides degree-linked experience guidance: Bachelor’s in Electronics Engineering with 2–3 years' relevant experience, or Master’s in Electronics Engineering with 1–2 years' relevant experience in emulation/prototyping contexts.

Responsibilities

Core responsibilities include customer support, migrations, training, and collaboration with R&D and sales.

  • Troubleshoot customer issues across partitioning, synthesis, place-and-route, and hardware debug on emulation and prototyping platforms.
  • Migrate customer designs to new software releases and resolve regressions or performance issues.
  • Deploy new software features on live customer designs and validate advanced partitioning and debug modes.
  • Deliver technical training from basic tool usage to advanced multi-FPGA partitioning and hardware-software co-verification.
  • Support pre-sales evaluations by running customer designs and demonstrating performance and limitations.
  • Collaborate with R&D to provide reproducible test cases and advocate for product improvements based on field experience.
  • Travel occasionally to customer sites for onsite support, training, or critical issue resolution.

Requirements

Must-have technical skills and behaviors:

  • Hands-on FPGA logic design and implementation experience, including synthesis, place-and-route, and timing closure.
  • Ability to read, debug, and modify RTL in Verilog, SystemVerilog, or VHDL.
  • Practical knowledge of FPGA architecture and backend flows: resource utilization, clock-domain crossing, and design partitioning.
  • Skilled at diagnosing issues from synthesis logs, waveform dumps, and utilization reports; able to reproduce issues and provide actionable context to R&D.
  • Customer-facing experience: communicate clearly under pressure, manage multiple customer issues, and deliver training.
  • Willingness to travel occasionally for customer support.

Nice-to-have:

  • Exposure to Xilinx or Altera (Intel) synthesis tools.
  • Familiarity with Synopsys emulation or prototyping hardware/software (Zebu, Protocompiler).
  • Experience with interface protocols such as PCIe, AXI, UART, or I2C.
  • Scripting for automation and log analysis (Python, Tcl, shell).

Education Requirements

Bachelor's degree in Electronics Engineering (with ~2–3 years' relevant experience) OR Master's degree in Electronics Engineering (with ~1–2 years' relevant experience), specifically in emulation or prototyping environments. No specific certifications were listed.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

Synopsys logo

Date Posted: 2026-09-16