Application Engineering, Sr Staff Engineer – Runset Development
SynopsysJob Title
Application Engineering, Sr Staff Engineer – Runset Development
Role Summary
Senior engineer on the physical verification team responsible for developing, validating, and optimizing verification runsets and rule decks for advanced process nodes. Work bridges foundries, customers, and Synopsys product teams to deliver production-ready verification flows that enable first-pass silicon success.
Experience Level
Senior — typically requires 5+ years of hands-on experience in physical verification, DRC/LVS rule deck development, or semiconductor layout verification.
Responsibilities
Key responsibilities include developing verification rule decks, automating runsets, debugging failures, and supporting customers and internal teams.
- Develop and validate DRC, LVS, Fill, ERC, and DFM rule decks for advanced process nodes (FinFET, GAA, sub-3nm).
- Translate foundry manufacturing rules into automated verification flows and partner with TSMC, Samsung, Intel Foundry, GlobalFoundries, and similar partners.
- Debug complex layout verification failures, identify root causes, and implement fixes to reduce silicon respins.
- Build automation frameworks and regression tests using Perl, Tcl, and Python to scale rule deck development and deployment.
- Optimize physical verification runsets across IC Validator, Calibre, and Pegasus for production use.
- Support customers and design teams to resolve verification issues and improve manufacturability compliance.
- Drive methodology improvements to improve runtime, accuracy, and verification efficiency.
Requirements
Must-have technical skills and experience; concise list of essentials and useful additions.
- 5+ years of hands-on experience in physical verification, DRC/LVS rule deck development, or layout verification.
- Strong scripting and automation skills in Perl, Tcl, and Python.
- Deep working knowledge of one or more physical verification platforms: IC Validator, Calibre, or Pegasus.
- Solid understanding of CMOS layout, ASIC design flows, and advanced semiconductor manufacturing processes.
- Proven ability to debug complex verification failures and deliver production-ready solutions under schedule pressure.
Nice-to-have:
- Experience supporting advanced technology nodes (7nm, 5nm, 3nm and below) or working directly with foundries on rule translations.
- Experience optimizing verification flows for large, production tapeouts and cross-platform environments.
Education Requirements
Bachelor's or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
