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Application Engineer II: Signal Integrity & Power Integrity

Cadence Design Systems
July 21, 2026
Full-time
On-site
Belo Horizonte, State of Minas Gerais, Brazil
EDA Jobs, Level - Mid-Career

Job Title

Application Engineer II: Signal Integrity & Power Integrity

Role Summary

Join the Global Customer Success team in Belo Horizonte to support customers deploying signal integrity (SI), power integrity (PI) and board design solutions. The role combines customer-facing support, debugging and optimization of high-speed systems, collaboration with R&D and field teams, and creation of technical documentation and best practices.

Experience Level

Mid-level (Application Engineer II). Years of experience not specified in the posting.

Responsibilities

Primary responsibilities include technical customer support, methodology development, and knowledge transfer.

  • Support customers in deployment, debugging, and optimization of SI/PI and board/package design flows.
  • Analyze system, board and package-level issues for high-speed interfaces and heterogeneous 3D-IC designs.
  • Drive methodology and solution-oriented discussions with customer stakeholders to increase tool adoption.
  • Collaborate with R&D, field teams, and product specialists to reproduce issues and verify fixes.
  • Develop technical documentation, examples, and knowledge base content to improve self-service and onboarding.
  • Mentor junior engineers and contribute to team technical capability.
  • Build relationships with worldwide teams to coordinate customer support and product feedback.

Requirements

Must-have technical skills and abilities for this role. Nice-to-have items are noted.

  • Must-have: Experience with system-level signal integrity and power integrity analysis and EM field-solver technologies.
  • Must-have: Familiarity with serial and parallel high-speed interfaces, channel simulation, equalization concepts, and measurement techniques.
  • Must-have: Ability to analyze 2D/3D signal waveforms, eye diagrams, eye density, and bathtub curves.
  • Must-have: Experience extracting and interpreting S-parameters; understanding of insertion loss, return loss, TDR, and RLGC.
  • Must-have: Basic experience with EDA environments and Linux-based workflows.
  • Must-have: Strong analytical, debugging, written and verbal communication skills in English; ability to work closely with customers and internal stakeholders.
  • Nice-to-have: Experience with EMI/EMC simulations and thermal analysis.
  • Nice-to-have: Prior mentorship experience and familiarity with board/package/3D-IC integration issues.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical field.


About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.

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Date Posted: 2026-07-20