Application Engineer Architect (STA SignOff)

Job Title

Application Engineer Architect (STA SignOff)

Role Summary

Senior technical role responsible for leading customer engagements to drive adoption and successful deployment of Cadence timing signoff and closure solutions across advanced process nodes.

The role partners with R&D and product teams to translate customer requirements into tool enhancements, optimizations, and production flows for STA, IR drop, power/timing closure, and related signoff domains.

Experience Level

Senior - requires extensive industry experience (15+ years) in IC implementation and signoff.

Responsibilities

Primary responsibilities include technical leadership with customers, cross-functional collaboration, and enablement of advanced signoff flows.

• Lead technical engagements with customers and partners to drive adoption of Cadence signoff portfolio.
• Guide design teams to meet customer success metrics for timing signoff and closure, including advanced-node flows and AgenticAI features.
• Collaborate with R&D and Product Engineering to influence product enhancements based on customer requirements.
• Develop and deploy complex benchmarks, flow optimizations, and methodologies for STA, IR drop, and power/timing closure.
• Provide thought leadership: present at industry forums, publish technical content, and represent the company externally.

Requirements

Must-have technical skills, domain expertise, and leadership abilities.

• 15+ years of experience in IC design implementation and signoff, with experience managing large technical programs.
• Deep expertise in digital design fundamentals, advanced-node STA and ECOs (3nm and below), and EDA tool ecosystems.
• Core timing signoff expertise: STA, UPF and constraints debugging, hierarchical and 3DIC STA and closure techniques.
• Proficiency in scripting and flow customization (Tcl, Python, Perl) for design closure.
• Proven ability to lead technical teams and influence stakeholders at executive levels; strong communication and negotiation skills.
• Prior experience with Cadence tools (Tempus, Certus, QRC) or competitive solutions is highly desirable.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related field (specified in posting).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.