Analog Mixed-Signal IC Design Engineer - Custom Digital Timing Characterization and Liberty Modeling (TeraWave)

Job Title

Analog Mixed-Signal IC Design Engineer - Custom Digital Timing Characterization and Liberty Modeling (TeraWave)

Role Summary

Work on TeraWave, a satellite communications network, to develop, simulate, characterize, and deliver Liberty (.lib) timing models and related collateral for custom digital and analog-digital interface circuits used in complex integrated circuits.

The role interfaces with analog designers, digital implementation, STA, verification, and physical design teams to ensure custom mixed-signal interfaces are accurately represented in digital timing flows.

Experience Level

Junior-level.

Responsibilities

Primary responsibilities include SPICE-level characterization, Liberty model generation, validation, and cross-functional integration.

• Generate and maintain Liberty (.lib) timing models for custom digital and analog-digital interface circuits.
• Define and characterize timing arcs: input-to-output delay, clock-to-Q, setup/hold, recovery/removal, minimum pulse-width, enable/disable, and conditional/tristate arcs.
• Characterize timing across PVT corners, input slew ranges, output loads, and parasitic-extracted conditions.
• Model pin capacitance, transition behavior, leakage, and dynamic power attributes required by Liberty.
• Validate .lib files against transistor-level simulations and downstream STA behavior (PrimeTime, Tempus, Innovus, Fusion Compiler, or equivalent).
• Build and maintain transistor-level SPICE testbenches; run SPICE/FastSPICE simulations and analyze waveforms to diagnose timing anomalies.
• Automate characterization flows and testbenches using scripting (Python, Tcl, Perl, shell, SKILL, etc.).
• Collaborate with layout and physical design teams to model parasitic impacts and support integration into synthesis, P&R, timing signoff, and verification flows.
• Document methodologies, produce timing characterization reports, and create reusable automation and templates.
• Mentor junior engineers on characterization, Liberty modeling, and SPICE validation.

Requirements

Must-have technical skills and constraints for the role.

• Significant hands-on experience in custom IC design, mixed-signal design, standard-cell characterization, or digital timing methodology.
• Practical experience with transistor-level simulation using SPICE-class tools (Spectre, HSPICE, Eldo, FineSim, XA, or equivalent).
• Strong understanding of CMOS digital circuit elements: inverters, combinational logic, latches, flip-flops, transmission gates, clocked logic, and reset/set structures.
• Demonstrated experience generating or validating Liberty (.lib) files and PVT-based characterization.
• Ability to analyze SPICE waveforms and debug circuit timing issues (non-monotonicity, races, glitches, metastability).
• Scripting experience for automation (Python, Tcl, Perl, shell, SKILL, or similar).
• Ability to work effectively across analog, digital, verification, STA, and physical design teams and communicate results clearly.
• Must be authorized to work in the United States per export-control requirements: U.S. citizen, U.S. permanent resident, or lawfully admitted refugee/asylee.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field preferred; posting also states 4+ years of relevant experience (i.e., degree and experience requirement expressed as minimum qualifications). Equivalent practical experience may be considered.

Preferred Qualifications

Nice-to-have skills and tool experience.

• Experience with Cadence Virtuoso, ADE Explorer/Assembler, Spectre, and analog/mixed-signal toolflows.
• Experience with library characterization tools (Cadence Liberate, Synopsys SiliconSmart, Solido, or custom flows).
• Familiarity with STA tools (Synopsys PrimeTime, Cadence Tempus) and post-layout/extracted-netlist simulations (DSPF, SPEF).
• Experience with level shifters, synchronizers, comparators, custom clocking circuits, CDC interfaces, metastability modeling, hysteresis, or threshold-crossing timing.
• Experience in advanced CMOS nodes and reliability/robustness analyses (aging, EM/IR, supply noise, mismatch, Monte Carlo, local variation).
• Ability to create Verilog, Verilog-A, SystemVerilog, or specify-block models to accompany Liberty timing models.

Compensation & Logistics

Base pay range for California applicants: $192,051.00 - $268,870.35 (annual). Relocation provided; travel up to 10% expected. Position is based on-site in San Diego (preferred) or Cupertino, CA; a temporary remote exception is approved while San Diego sites are developed.

Other

Background check required. Blue Origin is an Equal Opportunity Employer. Benefits include medical, dental, vision, life insurance, parental leave, disability, 401(k) match, stock options for regular employees, and paid time off.

About the Company

Company: Blue Origin

Headquarters: Kent, Washington, United States

Blue Origin is an American aerospace company developing technologies for spaceflight, including reusable launch vehicles, orbital and suborbital systems, and space infrastructure for commercial and government customers.