Analog/Mixed-Signal IC Design Engineer - Acacia (Hybrid)

Job Title

Analog/Mixed-Signal IC Design Engineer — Acacia (Hybrid)

Role Summary

Join the Acacia mixed-signal IC design team to architect, design, layout, measure and productize ultra-deep sub-micron CMOS analog/mixed-signal circuits for high-speed optical transceivers (100G–1.6T+). The team interfaces with digital/DSP, system, package and module design groups.

This is a hybrid role based in San Jose, CA (three days per week on-site).

Experience Level

Level: Senior. Typical experience: Bachelor's +8 years, Master's +6 years, or PhD +3 years of related experience.

Responsibilities

The engineer will lead design efforts, deliver high-speed analog/mixed-signal blocks, and support production qualification and lab validation.

• Architect, design, simulate, layout and validate high-speed AMS circuits and blocks for optical transceivers.
• Lead large-block design efforts on complex ASICs and track deliverables through production.
• Mentor and review work of other designers; participate in peer design reviews and drive design methodology.
• Collaborate with packaging and hardware teams to meet signal and power integrity requirements.
• Develop and execute lab validation, test setups, and characterization across PVT.
• Address manufacturability concerns including electromigration, self-heating, and IR drop.

Requirements

Must-have technical skills and experience. Candidates should satisfy most items and demonstrate depth in high-speed AMS design.

• Experience in design, simulation and measurement of high-speed ICs in at least three of the following areas: serializers/deserializers and data converters; high-performance output drivers; phase-locked loops (PLLs); clock distribution; op amps and programmable gain amplifiers; equalization techniques; system link modeling for link simulations.
• Hands-on experience with high-speed analog design targeting optical transceiver applications (backplane and cable communications preferred).
• Experience with high-frequency layout, including floorplanning for power/ground and analog/digital signal routing, and passive components (inductors, transformers, transmission lines).
• Proven ability to take designs from concept through silicon bring-up, characterization and production qualification.
• Strong problem-solving, attention to detail, and ability to work both independently and collaboratively in cross-functional teams.

Nice-to-have / preferred:

• Experience with FinFET and GAA process technologies.
• Experience with design-for-manufacturability methods and characterization over PVT.
• Laboratory validation experience, including ESD methodology and building test setups.
• Familiarity with Cadence Virtuoso, Spectre/SpectreX/APS, Virtuoso/Calibre layout validation, EMX, AMS mixed-signal simulations, and MATLAB.

Education Requirements

Minimum qualifications: Bachelor's degree plus 8 years of related experience, OR Master's plus 6 years, OR PhD plus 3 years of related experience. The posting specifies degree-level experience requirements but does not name specific fields of study.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).