Analog/Mixed-Signal IC Design Engineer

Job Title

Analog/Mixed-Signal IC Design Engineer

Role Summary

Design and develop analog and mixed-signal circuits as part of a new ASIC team building MEMS-based timing solutions. The role covers full-chip design activities from block specification through pre- and post-layout verification and post-silicon debug.

Work within a small cross-functional ASIC team reporting to the Director of ASIC; contribute technical leadership on analog system blocks and support integration with MEMS components.

Experience Level

Mid-level. Typical background per posting: MS with 5+ years relevant experience, or Ph.D. with 2+ years industry experience.

Responsibilities

The position is responsible for hands-on circuit design and verification across the ASIC lifecycle.

• Design analog and mixed-signal blocks for a full custom ASIC from architecture to tape-out.
• Develop block-level specifications, test plans, and verification methodology.
• Perform schematic design and Spice-based simulation for performance verification.
• Debug circuits pre- and post-layout to meet performance targets.
• Support post-silicon debug and ASIC/MEMS integration activities.
• Collaborate with layout, verification, and system teams on calibration and compensation strategies.
• Document designs, test results, and design-for-test considerations.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Proven analog-oriented circuit design experience (bandgap, regulators, data converters, clock generators, PLLs, switched-capacitor circuits).
• Good understanding of continuous- and discrete-time signal processing concepts.
• Proficiency with schematic capture tools such as Cadence Virtuoso or Synopsys Custom Compiler.
• Experience with Spice-based simulators (Spectre, HSpice, AFS) for analog verification.
• Solid knowledge of analog design flow, testing methodology, block-level specification, calibration and compensation techniques.
• Familiarity with layout design concepts: parasitics, matching, symmetry, gradient/proximity effects, and reliability considerations.

Nice-to-have:

• Scripting experience (Shell, Perl, Python, TCL).
• Analog modeling in Verilog or Verilog-A.
• Experience with Matlab and Simulink.

Education Requirements

Master's degree (MS) with 5+ years of relevant experience, or Ph.D. with 2+ years of industry experience as specified in the posting. No other degree or field-of-study requirement was stated.

About the Company

Company: Stathera

Fabless semiconductor company developing MEMS-based timing solutions and DualMode™ frequency technology to replace traditional quartz timing. The company works on precision timing and synchronization for electronics and is backed by investors including MediaTek, Seiko Epson, TXC, BDC Capital, and Celesta Capital.