Analog Mixed-Signal Design Engineer (NCG — PhD Graduate)

Job Title

Analog Mixed-Signal Design Engineer (NCG — PhD Graduate)

Role Summary

Design and verify advanced-node CMOS analog and mixed-signal circuits for high-speed connectivity applications. Work on blocks such as PLLs, ADCs, regulators, amplifiers, TX/RX, CDRs and clock distribution to meet performance, noise, and jitter targets.

Contribute as an individual technical owner across design, tapeout, and lab bring-up while coordinating with global teams and system architects.

Experience Level

Senior — requires demonstrated independent contributor experience; typically 2+ years working on complex analog/mixed-signal IC designs.

Responsibilities

Key responsibilities include:

• Architect, design, and simulate analog/mixed-signal circuits (PLL, DLL, ADC/DAC, regulators, op-amps, comparators, TX/RX, CDRs).
• Perform transistor-level design, feedback/stability analysis, and noise/jitter analysis to meet performance targets.
• Implement designs for advanced CMOS nodes (20 nm or newer) and drive tapeout activities.
• Bring up silicon in the lab: debug, characterize, and iterate on chip fixes and calibrations.
• Use industry-standard tools for circuit simulation and analysis (for example, Spectre and MATLAB) and develop scripts or models as needed.
• Collaborate with cross-functional and geographically distributed teams; produce documentation and technical presentations.

Requirements

Must-have technical skills and experience:

• 2+ years designing high-speed mixed-signal circuits, including ADC/DAC, RX front-ends, TX drivers/serializers, and low-jitter PLLs.
• Strong transistor-level design skills and fundamentals in biasing, band-gap/reference circuits, op-amps, comparators, and analog blocks.
• Proven track record implementing analog circuits for high-speed data transmission and working on TX/RX calibration or clock distribution.
• Design and tapeout experience in advanced CMOS nodes (20 nm or newer).
• Experience with lab chip bring-up and debugging.
• Proficiency with circuit simulation tools (e.g., Spectre) and MATLAB for analysis and verification.
• Strong independent problem-solving, communication, documentation, and teamwork skills under tight schedules.

Nice-to-have:

• Experience with TIA design and optical drivers, RFIC design for wireless or wireline systems.
• Familiarity with Python, Matlab scripting, or C; PCB design experience.
• Familiarity with Verilog RTL or DSP design concepts and optical transceiver knowledge.
• Expertise in ESD protection techniques and IC packaging methodologies; publications or patents in analog/RF IC design.

Education Requirements

Master's or PhD in Electrical Engineering is required; candidates should have a strong academic and technical background in EE. The posting expresses a preference for graduates from top-tier programs.

Compensation: Base salary range shown: $150,000 - $200,000 USD (Canada range listed separately: $110,000 - $130,000 CAD).

About the Company

Company: Astera Labs

Headquarters: Santa Clara, CA, United States

Astera Labs provides rack-scale AI infrastructure via semiconductor-based connectivity solutions and the COSMOS software suite, integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies. It offers standards-based and custom connectivity products for hyperscalers and data centers to enable scalable, high-performance AI systems.