Analog, Mixed-Signal & Circuit Design Intern (PhD)

Job Title

Analog, Mixed-Signal & Circuit Design Intern (PhD)

Role Summary

This is a Ph.D. internship embedded within Marvell's analog and mixed-signal design teams. Interns execute transistor-level circuit design work that feeds directly into production IP and research-stage silicon used in high-speed SerDes, silicon photonics, ADC/DACs, PLLs, and related analog systems.

Work includes the full design flow: architecture and schematic, simulation, layout coordination, post-layout verification, and silicon bring-up while collaborating with senior analog engineers and layout teams.

Experience Level

Entry-level internship for current Ph.D. candidates (doctoral interns). Prior hands-on analog/mixed-signal transistor-level design experience is required.

Responsibilities

Primary day-to-day responsibilities include:

• Design, simulate, and verify analog and mixed-signal circuit blocks across the full design flow (architecture → schematic → simulation → layout coordination → silicon bring-up).
• Work on production-grade IP such as high-speed SerDes building blocks, silicon photonics drivers/receivers, ADC/DAC architectures, PLLs, clock distribution, LDOs, and precision analog circuits.
• Use industry-standard tools for design and verification (Cadence, Spectre) and system-level tools (MATLAB or Python).
• Collaborate with layout engineers to implement designs and iterate based on parasitics and silicon feedback.
• Attend and contribute to design reviews; present and defend design decisions and tradeoffs to the engineering team.
• Participate in a structured analog design curriculum alongside other Ph.D. interns.

Requirements

Must-have technical skills and experience:

• Hands-on experience designing and simulating analog and mixed-signal circuits at the transistor level (PLLs, high-speed I/O, amplifiers, regulators, ADCs/DACs, or equivalent blocks).
• Proven ability to simulate and verify designs independently using Cadence Virtuoso, Spectre, or equivalent tools.
• Strong fundamentals in device physics, noise analysis, linearity, stability, and low-power analog techniques in advanced CMOS processes.
• Practical experience with MATLAB or Python for system-level modeling and analysis.
• Clear verbal and written communication skills for presenting technical work and tradeoffs.

Nice-to-have:

• Experience in FinFET process nodes (7nm, 5nm, 3nm).
• Familiarity with high-speed serial link architectures, optical transceiver circuits, or die-to-die interconnects.
• Exposure to layout-aware design, parasitic extraction, and post-layout simulation.
• Behavioral modeling experience in Verilog-A or similar languages.

Education Requirements

Currently enrolled in a Ph.D. program in Electrical Engineering or a closely related field with a research focus in analog, mixed-signal, or RF circuit design (doctoral candidate status required).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.