Analog Layout Staff Engineer

Job Title

Analog Layout Staff Engineer

Role Summary

Design and lead custom analog/layout blocks and IP (high-speed I/O, PLL/DLL, bandgap, clock trees, PHY macros) from schematic to verified layout. Work within a global mixed-signal team to integrate analog layouts into top-level designs and packages.

Primary mission: deliver high-performance, manufacturable analog layouts, improve layout flows, and mentor junior engineers.

Experience Level

Senior - requires at least 5 years of custom layout experience; expected to lead layout teams and mentor junior engineers.

Responsibilities

Deliver and integrate analog/custom layout blocks, ensure verification and manufacturability, and improve layout processes.

• Implement custom layout for analog IPs (High-Speed I/O, PLL/DLL, bandgap, PHY macros, clock trees).
• Floor planning, power network design, signal routing strategy, parasitic optimization, and EMIR-aware layout.
• Apply high-speed layout techniques to meet performance and area targets while maintaining yield.
• Develop and enhance layout flows to increase design quality and throughput.
• Perform layout verification: DRC, LVS, ERC, ANT, ESD, DFM; run PERC checks for ESD/LUP.
• Coordinate with place-and-route and package teams to integrate analog die into top-level and package designs (including interposer/RDL work).
• Participate in global design reviews and research projects for future flows and IP enhancements.
• Lead layout teams to complete full design blocks and mentor junior engineers and interns.

Requirements

Essential technical skills and experience required for successful performance in this role.

• 5+ years' hands-on custom analog layout experience.
• Proficiency with layout entry tools (Cadence, Synopsys).
• Experience with layout verification tools (Mentor Calibre, Synopsys ICV).
• Understanding of semiconductor fabrication processes and MOSFET fundamentals.
• Knowledge of high-speed layout techniques and reliability issues (ESD, latchup, antenna effects, EMIR).
• Experience leading/mentoring layout engineers and preparing layout review presentations and verification reports.
• Good English communication skills and ability to collaborate across global teams.

Education Requirements

Bachelor's degree (BS) in Electronics Engineering, Electromechanics, or Telecommunications is stated.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.