Analog Layout Staff Engineer

Job Title

Analog Layout Staff Engineer

Role Summary

The Analog Layout Staff Engineer is a member of the Central Engineering group responsible for physical implementation, verification, and delivery of analog and mixed-signal IP. The role partners closely with analog designers and global teams to produce floorplans, layouts, and perform verification until designs meet specifications.

Work is hands-on with emphasis on accuracy, delivery, and cross-functional collaboration across international teams.

Experience Level

Senior / Staff level. The team may consider candidates at different levels during interview; final level and offer will align to assessed experience.

Responsibilities

Core responsibilities include hands-on layout, verification, and cross-team collaboration.

• Perform analog layout and implementation using CAD tools, including Cadence Virtuoso, and run simulations and verifications.
• Collaborate iteratively with analog designers to refine and debug layouts until specifications are met.
• Take ownership of tasks across the development cycle: floorplan, layout, verification, delivery, and post-delivery support.
• Deliver high-speed and precision analog circuit layouts across process nodes and support portability across nodes where required.
• Participate in project meetings, provide technical updates, present issues and solutions to global stakeholders, and act as a technical mentor within the layout team.
• Work closely with distributed teams across time zones and support project priorities that may change in duration or focus.

Requirements

Must-have technical skills and workplace expectations.

• Fundamental understanding of electrical concepts and analog circuit behavior.
• Proficiency with layout and verification CAD tools; experience with Cadence Virtuoso preferred.
• Proven track record delivering high-speed or precision analog circuits; experience across multiple process nodes is desirable.
• Demonstrated ownership through full development cycle from cells to functional blocks or full interfaces/chips.
• Strong written and verbal communication skills for presenting status and collaborating with global teams.
• Ability to work onsite full time (five days per week) in the Pavia office.
• May require eligibility to access export-controlled technology; candidates could be subject to export license review.

Education Requirements

Graduate or undergraduate degree in Electrical Engineering (Bachelor's or Master's) is indicated in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.