Analog Layout Principal Engineer

Job Title

Analog Layout Principal Engineer

Role Summary

Principal analog custom layout engineer responsible for producing high-performance analog layouts for custom ICs and driving top-level integrations from design to volume production. Work is focused on High-Speed Connectivity, Broadband Analog and Computing/Storage-Memory Data-Transport products.

Lead and mentor layout engineers and collaborate with circuit designers, physical verification, and cross-site teams to deliver tape-outs in deep sub-micron and FinFET technologies.

Experience Level

Senior — principal-level role. Candidates typically have 8–15+ years of relevant analog layout experience depending on academic degree.

Responsibilities

Key responsibilities include:

• Create custom analog layouts from schematics using industry CAD tools in deep sub-micron and FinFET process technologies.
• Lead and manage a custom analog layout team; provide technical mentoring and guidance.
• Perform top-level integration and coordinate with place-and-route and system teams to deliver tape-outs to production.
• Collaborate with circuit designers to clarify layout requirements and recommend schematic or layout changes.
• Work with Physical Verification to analyze and close DRC, LVS, ANT, ERC, and EMIR issues.
• Document and present technical status, issues, and solutions to project teams and stakeholders.
• Coordinate with global teams and adapt to variable project durations and priorities.

Requirements

Must-have:

• Proven record of analog/custom layout in advanced CMOS and FinFET process nodes.
• Experience managing or leading a custom analog layout team and performing top-level integrations.
• Hands-on experience with Cadence Virtuoso (VXL) and/or Synopsys Custom Compiler.
• Experience with Mentor Graphics Calibre for DRC/LVS verification and PV closure workflows.
• Proven ability to deliver designs to production (tape-outs) and resolve manufacturing verification issues.
• Strong problem-solving, communication, presentation skills, and ability to work independently and in global teams.

Nice-to-have:

• Experience with multi-GHz ADC/DAC, PLL/DLL, high-speed serial/parallel I/O, and clock generation/distribution blocks.
• Prior experience supporting volume production and cross-functional system-level integration.

Education Requirements

Posting specifies degree-based experience bands: Bachelor’s degree in Computer Science, Electrical Engineering or related field with ~15+ years of related professional experience; Master’s degree in those fields with ~10–12 years of experience; PhD in those fields with ~8–10 years of experience. The posting does not explicitly state "or equivalent experience."

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.