Analog Layout Lead, Silicon Engineering

Job Title

Analog Layout Lead, Silicon Engineering

Role Summary

Lead the full‑custom physical implementation of analog and mixed‑signal blocks for Meta's VR/AR silicon. Define and enforce layout methodologies, drive verification closure, and coordinate with circuit, process, and packaging teams to meet power, performance, noise, and area targets.

US base salary range: $178,000–$250,000 per year (base), plus bonus, equity, and benefits.

Experience Level

Senior / Lead level. Typical requirement: 8+ years of full‑custom analog and mixed‑signal layout experience.

Responsibilities

Core responsibilities include:

• Lead full‑custom layout of analog/mixed‑signal blocks (PLLs, ADCs/DACs, LDOs, bandgaps, high‑speed I/O) from concept through tape‑out.
• Define and enforce analog layout methodologies, design rules, matching, shielding, and noise‑isolation best practices.
• Drive parasitic‑aware layout strategies and perform post‑layout analysis to resolve layout‑induced performance issues.
• Collaborate closely with circuit designers on LVS/LVS vs. schematic, LVS, parasitic extraction, and back‑annotation iterations.
• Own physical verification closure (DRC, LVS, antenna checks) on advanced process nodes and manage GDS delivery.
• Establish floorplanning and integration strategies for analog IP inside mixed‑signal SoCs.
• Provide technical leadership, review layouts, mentor engineers, and manage/coordinate external layout contractors.
• Partner with process technology and PDK teams to evaluate new nodes and contribute to PDK qualification.
• Develop long‑term physical design roadmaps and reusable layout assets.

Requirements

Must‑have qualifications and skills:

• 8+ years of hands‑on experience in full‑custom analog and mixed‑signal layout for production silicon on advanced CMOS nodes (28nm or below).
• 8+ years using industry‑standard layout tools such as Cadence Virtuoso for schematic‑driven layout, parasitic extraction, and physical verification.
• Proven experience leading layout of high‑performance analog blocks (PLLs, voltage regulators, data converters, high‑speed interfaces) through tape‑out.
• Experience defining and implementing layout methodologies for matching, shielding, and noise isolation in mixed‑signal environments.
• Experience collaborating with circuit designers to translate simulation requirements into layout constraints and implementation decisions.
• Experience managing and mentoring layout engineers and coordinating work with external contractors.

Nice‑to‑have:

• Familiarity with post‑layout simulation flows (RC extraction, back‑annotation) and tools such as Spectre or Calibre.
• Experience evaluating or contributing to PDKs and design rule documentation for new nodes.
• Analog layout experience for wearable, mobile, or IoT SoCs with strict power/area/reliability constraints.
• Experience with 3D stacking technologies and advanced packaging layout considerations.
• Track record developing reusable analog templates or parameterized cells to improve team efficiency.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.