Analog Layout Engineer

Job Title

Analog Layout Engineer

Role Summary

The Analog Layout Engineer is responsible for physical silicon layout of high-speed mixed-signal blocks (SerDes, ADC/DAC, PLLs and other high-speed analog/RF blocks). The role focuses on floorplanning, layout-dependent effects mitigation, parasitic/noise control, and manufacturable integration for advanced CMOS/FinFET processes.

Experience Level

Mid-level - typically 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes.

Responsibilities

Design and deliver manufacturable layouts for high-speed analog/mixed-signal circuits; ensure integration and reliability across chip and package boundaries.

• Create block-level and chip-top floorplans; manage hierarchical block integration and package-aware co-design (micro-bump, package constraints).
• Implement layout techniques to control parasitics and noise: device matching, common-centroid placement, guard rings, shielding and isolation strategies.
• Address layout-dependent effects (LOD, WPE, LDE) and optimize for device matching and signal integrity.
• Achieve closure on DRC, LVS, ERC and antenna rules; ensure EM/IR reliability and ESD protection requirements are met.
• Work with design, verification and back-end teams to integrate layout with timing, power and physical verification flows.
• Support tapeout readiness, sign-off activities and debug of post-layout issues.
• Be available to travel or be onsite at customer/Arrow client offices as requested.

Requirements

Must-have technical skills and experience for immediate contribution; nice-to-have items follow.

• 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes.
• Proven experience with advanced process nodes, explicitly including TSMC N3 and N5; lower-node (N3/N5) experience is critical.
• Strong track record closing physical verification: DRC, LVS, ERC, antenna, EM/IR and ESD requirements.
• Experience with layout techniques for high-speed blocks, device matching and parasitic/noise mitigation.
• Familiarity with package-aware layout and micro-bump co-design.
• Ability to collaborate across design, verification and back-end teams and to support tapeout activities.
• Must be able to travel to Arrow client office locations or be onsite when requested.
• Nice-to-have: direct experience laying out SerDes, ADCs/DACs, PLLs and other high-speed analog/RF blocks.

Education Requirements

Bachelor's degree.

About the Company

Company: eInfochips

Headquarters: Bengaluru, India

eInfochips is a product engineering and semiconductor design services company offering embedded software, SoC design and verification, testing, and IoT solutions. It operates as part of Arrow Electronics, serving clients across industries worldwide.