Analog IO Layout Design Senior Engineer

Job Title

Analog IO Layout Design Senior Engineer

Role Summary

The engineer is responsible for physical layout design and development of analog IO/physical IP (examples: SERDES, DDR, memory) within the Logic Libraries team, working on advanced technology nodes.

Works closely with globally distributed product, QA and customer engineering teams to implement, optimize and validate layouts, apply CMOS fundamentals and device-physics understanding, and automate design flows where possible.

Experience Level

Mid-level (position title: Senior Engineer). Typical experience in posting: BSEE + 3+ years or MSEE + 1+ years of relevant ASIC/IP verification experience.

Responsibilities

Primary responsibilities include hands-on layout design, cross-team collaboration, and process automation.

• Design and develop physical IP blocks (e.g. SERDES, DDR, memory) and associated layout for logic libraries.
• Collaborate with global teams to implement and optimize layouts on advanced nodes.
• Apply CMOS fundamentals and semiconductor device-physics knowledge to ensure manufacturable, high-quality layouts.
• Use Unix/Shell/Python/TCL scripting to automate and improve design workflows.
• Conduct and participate in design reviews, provide technical feedback and iterate on designs.
• Stay current with industry trends and technology node advancements relevant to physical IP design.

Requirements

Key technical skills and attributes required or strongly preferred.

• Must-have: Strong understanding of semiconductor device physics and digital design principles.
• Must-have: Solid foundation in CMOS fundamentals and proficiency in layout design for physical IP.
• Must-have: Experience with Unix/Shell scripting; familiarity with Python and TCL.
• Must-have: Proven ability to work collaboratively with geographically distributed teams and communicate effectively.
• Must-have: Detail-oriented with strong analytical and problem-solving skills.
• Nice-to-have: Direct experience designing SERDES, DDR, or memory IP and working on the latest technology nodes.
• Nice-to-have: Experience automating layout/verification flows and contributing to process improvement.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) with 3+ years relevant ASIC/IP verification experience, or Master of Science in Electrical Engineering (MSEE) with 1+ years relevant ASIC/IP verification experience (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.