Analog Design Engineer, Principal

Job Title

Analog Design Engineer, Principal

Role Summary

Principal analog design engineer on the Central Engineering - Optical PHY (CE-OPHY) team based in Pavia, Italy. Responsible for transistor-level design, modeling, layout supervision, lab characterization, and ownership of analog macros/IP used in high-speed optical transceivers. This is a full-time on-site role collaborating with cross-functional teams and mentoring junior designers.

Experience Level

Senior — experience guidance provided by the employer: Master’s +10+ years or PhD +7+ years of relevant work experience.

Responsibilities

Primary responsibilities include:

• Analyze block specifications and select appropriate circuit topologies.
• Design analog blocks at the transistor level and take ownership of entire analog macros/IPs.
• Supervise custom analog layout, provide guidelines, and perform post-layout verification.
• Model circuit blocks and validate models against specifications.
• Collaborate with other teams to integrate and enhance solutions.
• Perform IC performance measurement, lab characterization, and debugging to correlate simulations with silicon measurements.
• Participate in cross-functional meetings, document designs, and mentor junior designers.

Requirements

Must-have skills and experience:

• Proven track record of independently designing ICs with full macro/IP ownership (architecture through lab characterization).
• Strong analog transistor-level design skills, preferably at multi-GHz frequencies.
• Extensive experience in analog custom layout and post-layout verification.
• Proficiency with EDA/CAD tools.
• Experience in IC measurement and debugging to align simulations with real measurements.
• Strong communication, presentation, and documentation skills.
• Proficiency in spoken and written Italian and English (minimum B2 level).

Nice-to-have:

• Direct project experience with multi-Gbps electrical SerDes or electro-optical transceivers.
• Experience with advanced CMOS nodes, including FinFET technologies.

Education Requirements

Master's degree in Electrical Engineering (preferably Microelectronics) with 10+ years of relevant experience, or PhD in Electrical Engineering (preferably Microelectronics) with 7+ years of relevant experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.