AI Silicon Physical Design Engineer
CerebrasJob Title
AI Silicon Physical Design Engineer
Role Summary
Join the physical design team to execute block- and full-chip physical implementation for high-speed AI silicon. The role owns synthesis, placement, routing, verification, timing closure, and integration of blocks into the full-chip floorplan while collaborating closely with RTL and architecture teams.
Experience Level
Senior — 10+ years of physical design and physical verification experience.
Responsibilities
Deliver physical design and verification of high-performance ASIC blocks and integrate them into full-chip builds.
- Synthesize, place, and route high-speed blocks and subsystems.
- Perform block, partition, and full-chip timing closure and STA.
- Resolve block and full-chip DRC and LVS issues using ICV or Calibre.
- Perform IR/EM analysis and implement fixes.
- Contribute to full-chip floorplanning and integration activities.
- Work with RTL teams to optimize microarchitecture for physical design.
- Develop and improve physical design flows via scripting and automation.
Requirements
Must-have technical skills and experience.
- 10+ years of physical design and physical verification experience.
- Strong knowledge of block-level and full-chip PD verification methodology.
- Proven experience in block/subsystem timing closure and full-chip timing convergence.
- Expertise in power, performance, and area optimization.
- Experience across the complete physical design flow (synthesis through signoff).
- Expert with ICV or Calibre for DRC/LVS resolution.
- Expertise in IR/EM analysis and remediation.
- Strong STA skills, constraint drafting, and timing convergence at block, partition, and full-chip levels.
- Proficiency in scripting (Tcl and Python) to enhance flows and automation.
- Experience with Design Compiler, Fusion Compiler, ICC2 (or equivalent physical design tools).
- Demonstrated ownership, deep technical problem solving, and ability to drive complex integration tasks.
Preferred:
- Experience or familiarity with CPU/GPU design.
- Block/partition PD, PDV experience is a plus.
- Familiarity with the Synopsys tool suite is a plus.
Education Requirements
Bachelor's or Master’s degree in Electrical Engineering.
About the Company
Company: Cerebras
Headquarters: Sunnyvale, CA, USA
Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.
