AI Silicon Performance Modeling and Analysis Engineer

Job Title

AI Silicon Performance Modeling and Analysis Engineer

Role Summary

Develop and maintain SystemC/TLM performance models to evaluate and guide architecture and product decisions for AI silicon platforms. Work with architects, design teams, and product stakeholders to analyze communication fabrics, memory subsystems, interconnects, and end-to-end data movement.

Primary focus: model development, validation/correlation, performance characterization, data analytics/visualization, and cross-functional technical leadership.

Experience Level

Mid-level - requires substantial industry experience. The posting specifies 6+ years of relevant industry experience.

Responsibilities

Key responsibilities include model development, validation, performance characterization, analytics, and stakeholder engagement:

• Design, implement, and enhance SystemC/TLM-based performance models for SoC fabrics, memory controllers, host-device paths, and scale-up/scale-out interconnects.
• Improve model fidelity, scalability, maintainability, and simulation performance; perform debugging and root-cause analysis of anomalies.
• Define and execute validation strategies, regression suites, coverage methods, and correlate models with reference simulations and hardware measurements.
• Run performance studies across workloads and configurations; analyze bandwidth, latency, congestion, buffering, and resource utilization; identify bottlenecks and quantify impact.
• Develop automated data collection, processing, analysis workflows and visualization dashboards; define and track performance KPIs and architectural metrics.
• Partner with architects, stimulus teams, silicon designers, and product stakeholders; present findings and influence architecture/product decisions.
• Drive methodology improvements, automation, and team knowledge sharing; mentor junior engineers and promote engineering best practices.

Requirements

Must-have technical skills and experience; preferred skills follow.

Must-have:

• 6+ years industry experience in performance modeling, AI silicon/SoC architecture, or performance engineering.
• Hands-on experience with SystemC and Transaction-Level Modeling (TLM).
• Proficient in C++ for model and simulator development.
• Working proficiency in Python for automation, data processing, analysis, and visualization.
• Experience with memory subsystem architecture (memory controllers, cache, latency/bandwidth characterization) and on-chip communication fabrics/NoC concepts.
• Experience developing, validating, and correlating performance models against simulations or hardware measurements.
• Ability to perform architectural tradeoff analysis, performance debugging, and scalability studies for scale-up and scale-out architectures.
• Strong analytical, communication, presentation, and cross-functional leadership skills.
• This position is not eligible for Intel immigration sponsorship.

Nice-to-have:

• Deep knowledge of AI accelerator architectures, distributed AI systems, and large-scale AI infrastructure.
• Experience with workload characterization, performance stimulus generation, and modeling of remote/host memory paths.
• Familiarity with dashboarding tools (Power BI, Tableau, Grafana, Plotly) and large-scale data analytics.
• Experience mentoring engineers and leading cross-functional technical projects.

Education Requirements

Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or Electronics Engineering is required per the posting.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.