AI Silicon, DFT Engineer

Job Title

AI Silicon, DFT Engineer

Role Summary

As a Member of Technical Staff, DFT Engineer, you will design and implement test architectures for novel AI-focused silicon. You will work on multi-disciplinary R&D teams to ensure complex digital logic and custom mixed-signal blocks are testable and producible.

Main responsibilities include DFT architecture and implementation, sign-off and verification, hierarchical DFT for large SoCs, and collaboration with foundries and partners to improve yield and test coverage.

Experience Level

Senior - typically 10+ years industry experience in digital DFT and test architecture; experience with modern process nodes (7nm, 5nm, or newer) preferred.

Responsibilities

Deliver and verify DFT solutions across SoC and advanced packaging contexts.

• Design and implement scan compression, MBIST, JTAG/boundary-scan, and other test logic using industry CAD tools.
• Develop hierarchical DFT methodologies: core-level wrapping, pattern retargeting, and top-level integration.
• Define DFT strategy with foundries; analyze defect densities and drive yield improvements for test chips.
• Develop DFT approaches for 2.5D/3D multi-stacked die and die-to-die interface coverage (e.g., IEEE 1838).
• Create test strategies for analog/mixed-signal macros integrated with digital fabric.
• Lead ATPG, fault simulation, test vector validation, and ensure timing closure for test modes.
• Optimize test coverage, test time, and yield while influencing micro-architecture for PPA.
• Develop and automate methodology and flows; set best practices for first-pass silicon success.
• Evaluate and engage external partners and AI tools to improve chip design efficiency.

Requirements

Required technical skills and experience for the role.

• 10+ years experience in digital DFT and test architecture with successful tapeouts on advanced nodes (7nm, 5nm, or newer).
• Deep knowledge of scan compression, MBIST generation, ATPG, and fault modeling (stuck-at, transition, path delay).
• Experience with static timing analysis (STA) and timing closure for shift and capture test modes.
• Expertise with standard EDA/DFT tool suites for DFT implementation and vector generation.
• Strong scripting skills (Tcl, Python, or Perl) to automate design flows and data analysis.
• Proven communication skills and experience managing deliverables from external vendors or design houses.

• Hands-on experience with die-to-die interconnect test strategies, chiplet testing, or 3D-IC DFT.
• Experience with test architecture for ML accelerators or large-scale systolic arrays.
• Experience integrating large custom analog macros and complex power-sequencing requirements.
• Familiarity with AI tools applied to chip design.

Education Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Unconventional AI

Headquarters: Mountain View, CA, United States

Unconventional AI is a startup developing a radically more energy-efficient computing platform for AI by mapping neural networks directly to semiconductor device physics, aiming for orders-of-magnitude efficiency improvements through novel chip architectures and mixed-signal integration.