AI/ML Silicon Accelerator Memory Architect

Job Title

AI/ML Silicon Accelerator Memory Architect

Role Summary

Define the end-to-end memory and data-transport architecture for AI/ML accelerators across multiple silicon generations. Own memory technology selection, controllers, on-die networks, DMA/gather-scatter engines, and scratchpad/cache microarchitecture to meet performance, capacity, and energy targets.

Collaborate with internal SoC teams and external memory/IP vendors to make quantified trade-offs between performance, power, area, and cost.

Experience Level

Senior - Principal/Distinguished Architect level. Requires 18+ years of ASIC/SoC architecture experience focused on memory systems and data movement.

Responsibilities

Key responsibilities include ownership of memory and data-movement architecture across product generations and driving implementation-ready specifications.

• Define multi-generation memory strategy (HBM, DDR/LPDDR/GDDR, on-die SRAM hierarchies, scratchpads) and associated capacity, bandwidth, and latency targets based on real AI workloads.
• Specify memory controller and cache/scratchpad microarchitecture: scheduling, address mapping, QoS, coherency, and consistency behavior across compute, DMA, and host traffic.
• Architect on-die interconnect topology, flow control, deadlock avoidance, and QoS for mixed traffic patterns feeding MACs.
• Design DMA, gather/scatter, layout-transform, multicast, and buffer-management engines with energy-per-bit (pJ/bit) as a primary constraint.
• Create analytical and simulation models to quantify latency, throughput, utilization, scalability, and trade-offs to guide architectural decisions.
• Drive co-architecture and integration with internal blocks and external memory/IP vendors across multiple silicon generations.

Requirements

Must-have technical skills, domain knowledge, and experience required for successful performance in this role.

• 18+ years of ASIC/SoC architecture experience focused on memory subsystems and data movement for HPC or AI workloads.
• Deep technical knowledge of memory subsystems: HBM, DDR/LPDDR/GDDR, controller design, cache coherency, memory consistency models, and tiered/pooled memory architectures.
• Proven ownership of data-movement architecture including on-die interconnects, DMA/copy engines, buffer hierarchies, and dataflow integration with compute blocks.
• Practical understanding of what common protocols cost in latency, area, and power (examples: NVLink, UALink, RDMA, ARM CHI, UCIe, PCIe).
• Strong performance-modeling and system-level simulation skills; ability to produce first-principles latency/throughput/utilization analyses.
• Experience producing implementation-ready specifications and driving cross-functional integration to silicon.
• Nice-to-have: experience with AI-specific workload characteristics (KV-caches, MoE sparsity, large-model dataflows) and multi-generation roadmap planning.

Education Requirements

MSEE/MSCE or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent demonstrated architectural impact or equivalent practical experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.