Advanced Packaging SI/PI Engineer

Job Title

Advanced Packaging SI/PI Engineer

Role Summary

Responsible for the electrical performance of an AI accelerator platform across silicon, package, and board. Work with silicon, package, platform, and system teams and external OSAT/ODM partners to define and deliver power delivery networks and high-speed signaling in advanced packaging.

Role is based in San Jose (Santana Row) and is fully in-person.

Experience Level

Senior — requires 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.

Responsibilities

Primary responsibilities include analysis, co-design, and ownership of SI/PI and PDN deliverables across package, substrate, and board.

• Perform SI/PI analysis and optimization for 2D/2.5D/3D package designs.
• Collaborate with package layout designers, ASIC PD/IP teams, and board schematic/layout teams to optimize electrical performance.
• Drive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out.
• Define PDN design and decoupling strategy across substrate and interposer; own DC IR drop, dynamic IR drop, and impedance targets across rails.
• Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package and board teams.
• Support board-level SI/PI and rack-level scale-up topology studies, including test vehicle design and cable characterization.
• Participate in cross-functional meetings and design reviews; present risks and sign-off status to leadership.

Requirements

Key must-have skills and experience; followed by relevant nice-to-have qualifications.

Must-have

• 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.
• Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis.
• Experience with high-speed interfaces such as HBM, SerDes, and die-to-die (D2D) interfaces.
• Hands-on expertise with one or more tools: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), or Keysight ADS.
• Experience with CoWoS or equivalent advanced packaging technologies, including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs.
• Track record of designing and correlating SI/PI test vehicles with silicon measurement during bring-up and lab characterization.
• Strong analytical and communication skills; able to present trade-offs and sign-off status to cross-functional leadership.

Nice-to-have

• Familiarity with full RTL-to-GDSII flow and interactions between PD, package, and board PDN.
• Experience with multi-die, 2.5D, or 3D packaging signoff and chip-package-system co-design.
• Project management experience coordinating internal teams, OSAT partners, and PCB ODMs.
• Familiarity with ML/LLM model architectures, accelerator architectures, or HPC system design.
• Startup experience or comfort working in a fast-paced environment.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is required (as stated). No certifications or equivalency language was specified.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.