Advanced Package Technology, Distinguished Engineer

Job Title

Advanced Package Technology, Distinguished Engineer

Role Summary

Lead development of advanced packaging technologies and architecture for high-performance computing, AI accelerators, and networking products. Responsible for defining packaging roadmaps, creating proof-of-concept technologies, driving co-design with silicon teams, and partnering with OSATs and foundries to enable manufacturable, reliable packages (2.5D/3D, interposers, co-packaged solutions).

Works across signal, power, thermal and mechanical domains to optimize package performance, select materials and processes, and transition technologies into production.

Experience Level

Senior — technical leader or senior individual contributor. The role requires extensive industry experience (see Education Requirements for degree-dependent years).

Responsibilities

Core responsibilities include technology strategy, design leadership, and supplier engagement.

• Develop packaging technology roadmap and define package architecture, chiplet topology, interposer/substrate scaling, PDN strategy, and thermal envelope.
• Initiate and advance new packaging concepts into proof-of-concept samples and productized technologies; create and protect IP.
• Perform routing feasibility, signal and power integrity studies, and co-design with silicon floorplanning and PDN modeling.
• Lead material selection, substrate stack-up definition, mechanical modeling, and reliability analysis.
• Partner with OSATs, substrate manufacturers and foundries to assess process capability, manufacturability, yield, and cost; drive qualification and reliability validation to volume readiness.
• Manage cross-functional programs and influence internal stakeholders and external vendors to align roadmaps and deliverables.

Requirements

Must-have technical skills, tools, and experience. Degree and years of experience are listed under Education Requirements.

• Extensive experience in advanced package and substrate technologies, component and board-level reliability, warpage and thermal management, and managing material and manufacturing vendors.
• Deep knowledge of electrical engineering concepts, circuit extraction and simulation, and design methodology for 2.5D/3D packages.
• Hands-on experience with signal and power integrity analyses and tools such as Cadence Sigrity PowerSI and Ansys SIwave; EM simulation experience with Ansys HFSS, Cadence Clarity (or equivalents) and ability to correlate simulations with measurements.
• Routing feasibility and package/PCB layout experience using Cadence APD or PCB editors; understanding of chip-package interactions and failure mechanisms.
• Program management skills for cross-functional initiatives; strong communication, presentation and documentation abilities; ability to work with global stakeholders.
• Ability to develop concepts into productizable technologies and to set technical roadmaps.
• Nice-to-have: prior experience with data-center AI accelerators, networking or HPC silicon; silicon disaggregation/reaggregation and memory integration; VNA/TDR measurements; demonstrated leadership driving supplier programs.

Education Requirements

Degree and experience combinations specified in the posting: Bachelor's degree in mechanical engineering, materials science or a related field with 20+ years of related professional experience; Master's degree with 15+ years of related experience; PhD degree or post‑doc with 12+ years of related experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.