3rd Party IP Technical Lead

Job Title

3rd Party IP Technical Lead

Role Summary

The 3rd Party IP Technical Lead owns integration and technical support of third‑party memory/SerDes PHY and mixed‑signal IP across multiple AMD SoC programs, coordinating with IP vendors, SoC integration teams, package/PCB, and post‑silicon validation groups.

Work covers IP architecture, design transfer, integration, post‑silicon bring‑up, validation, and production support. Primary location is Markham, ON, Canada; role is open to Vancouver, BC and Ottawa, ON.

Experience Level

Senior (Lead). The posting expects advanced technical leadership and independent problem solving; no explicit years-of-experience stated.

Responsibilities

The role provides technical ownership and lifecycle leadership for selected third‑party PHY and mixed‑signal IP across products.

• Act as AMD technical owner for selected third‑party Memory/SerDes PHY and mixed‑signal IP across multiple programs.
• Lead IP lifecycle: architecture, design transfer, integration, post‑silicon validation, and production support.
• Collaborate with third‑party IP vendors on evaluation, design transfer, release collateral, and integration.
• Partner with SoC integration teams to ensure electrical, logical, and physical quality of IP integration.
• Drive system‑level architectural tradeoffs for performance, power, area, cost, and implementation constraints.
• Translate industry standards and customer requirements into silicon, package, PCB, and validation specifications.
• Support package and PCB teams on signal integrity (SI) and power integrity (PI) analysis, debug, and optimization.
• Coordinate post‑silicon bring‑up, debug, characterization, compliance testing, and production test support.
• Analyze post‑silicon results and recommend improvements to PHY architecture and development processes.
• Evaluate new PHY and mixed‑signal IP technologies for licensing and adoption.

Requirements

Must-have technical skills and experience; preferred items are noted.

• Proven experience integrating third‑party PHY and mixed‑signal IP into SoCs and supporting IP across the product lifecycle.
• Strong knowledge of high‑speed I/O SerDes or memory PHY architectures and related blocks (CTLE, FFE, DFE, VGA, CDR, PLL/DLL, TX driver, EMC, GPIO).
• Experience with system‑level architecture decisions and balancing performance, power, area, and cost.
• Experience supporting package/PCB SI and PI and working with SI/PI experts to debug and optimize designs.
• Post‑silicon validation experience: bring‑up, debug, characterization, compliance testing, and ATE production test support.
• Familiarity with RTL, logic design, and digital circuits.
• Comfortable in UNIX environments; scripting with Python and/or Perl desirable.
• Hands‑on lab experience with equipment such as BERT, oscilloscope, and logic analyzer is desirable.
• Experience with advanced FinFET technologies (7nm and below) preferred.
• Strong analytical skills, attention to detail, and effective verbal/written communication.

Education Requirements

B.S. or M.S. in Electrical Engineering preferred (posting lists these degrees). No explicit alternative-equivalent-experience language was provided in the posting.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.