Synopsys VC SpyGlass Lint Engineer Jobs: Browse RTL QA Roles
VC SpyGlass lint-clean RTL is a standard sign-off gate before synthesis at most large semiconductor companies. These roles go to IC design engineers who run Synopsys VC SpyGlass, the RTL static analysis platform that started life as Atrenta SpyGlass and now sits inside the Synopsys VC Static suite.
The day-to-day work is running Lint and CDC flows, then keeping them clean as the RTL churns. You maintain goal files that hold design-specific rule configurations, create and justify waivers for false positives, and wire SpyGlass runs into the sign-off flow so nothing reaches synthesis with an open violation. RDC, DFT, and power-intent checks often land on the same engineer.
Depth matters more than breadth here. A hiring manager wants someone who has taken a design through a full tapeout with the tool, not someone who has clicked through a tutorial. CDC engineer roles and RTL design positions sit right next to this one, and many engineers move between all three over a career.
Which companies hire for it depends on their EDA stack. Synopsys-primary shops run VC SpyGlass as the default gate, while mixed-vendor teams may pair it with Cadence or Siemens flows further down the line. Reading a company's tool ecosystem before you apply tells you which sign-off methodology you will actually be defending in the interview. If you want to see the wider tooling market, the EDA jobs category lists roles across vendors.
When you write up your experience, be concrete: which blocks you signed off, what waiver policy you set, how you cut noise out of the goal files, and any methodology scripts you wrote. That narrative beats a generic "familiar with SpyGlass" line every time. Vendor user groups like SNUG and CDNLive are also worth tracking for early visibility into new checks and analysis features.
Save a search on semidesignjobs.com and you will get an email when a VC SpyGlass role opens that matches your filters.
FAQ
What is the difference between VC SpyGlass and standalone SpyGlass (Atrenta)?
Synopsys acquired Atrenta SpyGlass in 2014 and folded it into the VC Static (Verification Compiler Static) suite as VC SpyGlass. The underlying analysis engines are the same. VC SpyGlass gains tighter integration with the Synopsys EDA platform and regular updates that track the VC product roadmap. Legacy references to SpyGlass or Atrenta SpyGlass point to the same technology.
What is RDC analysis in VC SpyGlass and how does it differ from CDC?
RDC (Reset Domain Crossing) analysis looks at signals crossing between different reset domains, where two flip-flops share a data path but get reset by different reset signals. Bad RDC can cause initialization failures if one domain leaves reset before another, producing metastability or data coherency bugs that only show up during power-up sequences.
How do waiver files work in VC SpyGlass lint flows?
SpyGlass waiver files hold exceptions for specific violations that have been reviewed and accepted, usually false positives from over-eager rules or intentional design patterns that break a style guideline for a good reason. Waivers reference rule names and RTL instance paths and require justification text for audit traceability. Waiver files stay version-controlled alongside the RTL.