CDC Engineer Semiconductor Jobs: Find Clock Domain Roles
Clock domain crossing defects are among the most difficult functional bugs to expose in simulation. A signal that passes every RTL test can still cause intermittent metastability in silicon when it crosses an asynchronous boundary under real PVT conditions. Modern SoCs routinely span 20 to 50 independent clock domains; CDC engineers are responsible for catching every structural violation before the design goes to fab.
The core work is structural and functional CDC analysis using Synopsys VC SpyGlass CDC, Cadence JasperGold CDC App, or Siemens Questa CDC. Beyond running the tools, engineers classify violations, define synchronization schemes (two-flop synchronizers, handshake protocols, async FIFOs), review synchronizer RTL, and establish project-level CDC sign-off criteria. On a complex mobile SoC or data center chip, a thorough sweep can surface hundreds of flagged crossings per iteration before the design is considered clean.
Formal verification experience makes a CDC engineer significantly more useful. The role bridges both ends of the design flow: structural CDC requirements get communicated to RTL design engineers early in a project, while functional CDC closure coordinates with verification engineers during sign-off. On large tapeout teams, CDC engineers often run automated checks nightly and triage results with RTL and DFT teams in the same review cycle.
Qualcomm, MediaTek, and Marvell hire CDC engineers for mobile and networking SoCs with complex multi-clock topologies. AI chip startups and hyperscaler in-house teams running high-speed designs staff this function as SoC complexity grows. At larger companies, the role typically sits within a design methodology or SoC verification group; at smaller fabless startups, the same engineer often owns CDC methodology end to end, working closely with the SoC integration team to reach full-chip sign-off.
Compensation for experienced CDC engineers at senior level runs in the $150K to $190K base range at established semiconductor companies, with higher total comp packages at well-funded AI chip startups. The salary guide on semidesignjobs.com has current market data by role level and company type.
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FAQ
What is clock domain crossing and why is it a concern in semiconductor design?
Clock domain crossing occurs when a signal generated in one clock domain is sampled by logic clocked by a different, asynchronous clock. Without proper synchronization, metastability can cause unpredictable chip behavior that passes simulation but fails in silicon, often under specific timing or temperature conditions.
What tools are used in CDC engineer semiconductor jobs?
Synopsys VC SpyGlass CDC, Cadence JasperGold CDC App, and Siemens Questa CDC are the most widely used tools for automated CDC analysis. They perform structural checks to identify unsynchronized crossings and flag missing or incorrect synchronizers across the full SoC hierarchy.
How does CDC analysis differ from formal verification in semiconductor jobs?
CDC analysis focuses on structural checks for clock domain crossings and synchronization correctness. Formal verification uses mathematical proof techniques to verify functional properties more broadly. The two are complementary disciplines often run in parallel on the same SoC, particularly on safety-critical automotive and AI accelerator designs.