Siemens Tessent DFT Engineer Positions: Browse Test Roles
Tessent is the design-for-test backbone at a large share of fabless and IDM teams, and Siemens EDA keeps it there by covering the whole test flow in one platform: scan insertion, ATPG, memory BIST, IEEE 1687 IJTAG, logic BIST, and embedded analytics for in-field monitoring. A Siemens Tessent DFT engineer owns that flow from RTL handoff through ATE pattern sign-off.
Day to day, the work runs on Tessent Shell scripting to automate the DFT flow. You insert scan chains and compression with Tessent Scan, generate patterns with Tessent FastScan, and stand up memory test with Tessent MemoryBIST. Building and debugging an IJTAG network for hierarchical test access is where the harder problems live, and it is the skill that separates a Tessent specialist from someone who has only run canned flows.
Tessent and Synopsys TestMAX are the two platforms that dominate ATPG and scan insertion. Most postings that name Tessent expect you to own the EDT compression setup and hit fault coverage targets inside the ATE test-time budget, not just launch the tool.
Companies pick a DFT platform and stay with it, so Tessent openings cluster at shops with an existing Siemens EDA relationship. Large fabless SoC teams, IDMs running their own fabs, and AI accelerator startups that cannot afford a test-methodology stumble all hire for it. Before you apply, check whether the employer runs a Cadence-primary, Synopsys-primary, or mixed-vendor flow; it tells you which tools you will actually touch.
US Tessent DFT roles at the mid level generally run about $140K to $185K base. Staff and principal DFT engineers at large fabless companies reach $220K to $300K in total comp. The semiconductor salary guide has wider ranges across DFT and adjacent roles.
The broader DFT engineer positions category on semidesignjobs.com lists current Tessent-tagged roles, and there are senior DFT openings if you are past the mid-career mark. Save a search and you will get an email when a matching role opens.
FAQ
What is Tessent Scan and how is it used in DFT engineer positions?
Tessent Scan inserts scan flip-flops into the netlist, stitches the scan chains, sets up EDT scan compression, and generates the scan SDC constraints. It produces the DFT-modified netlist that goes to place-and-route and feeds later ATPG runs. In practice it is the first Tessent step you run after synthesis, and its output defines the test structure the rest of the flow depends on.
What is the EDT (Embedded Deterministic Test) methodology in Tessent?
EDT is Tessent's on-chip scan compression. A hardware decompressor and compressor let you apply far more patterns in the same test time. EDT cuts test data volume and test time by roughly 10x to 100x versus uncompressed scan, which is what makes high fault coverage affordable inside the ATE test-time budget on a large SoC.
How does Tessent IJTAG work for hierarchical DFT access?
Tessent IJTAG, based on IEEE 1687, builds a hierarchical network of test data registers and scan segments reached through one JTAG TAP. It gives independent access to embedded instruments such as memory BIST controllers, on-chip monitors, and debug registers at any level of the hierarchy, without routing hundreds of dedicated test wires to the top-level pins.